From 608641e23c7f2288810c3f23a1a63790b664f2ab Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Sun, 26 Jul 2015 10:21:20 -0500
Subject: cpu: implements vector registers

This adds a vector register type.  The type is defined as a std::array of a
fixed number of uint64_ts.  The isa_parser.py has been modified to parse vector
register operands and generate the required code.  Different cpus have vector
register files now.
---
 src/arch/power/isa.hh | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/arch/power/isa.hh')

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index aaf5bd92a..08ee82d5d 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -105,6 +105,13 @@ class ISA : public SimObject
         return reg;
     }
 
+    // dummy
+    int
+    flattenVectorIndex(int reg) const
+    {
+        return reg;
+    }
+
     int
     flattenMiscIndex(int reg) const
     {
-- 
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