From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001 From: Yasuko Eckert Date: Tue, 15 Oct 2013 14:22:44 -0400 Subject: cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. --- src/arch/power/registers.hh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/arch/power/registers.hh') diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index 89de3719c..abee516fc 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -52,6 +52,9 @@ typedef uint64_t FloatRegBits; typedef double FloatReg; typedef uint64_t MiscReg; +// dummy typedef since we don't have CC regs +typedef uint8_t CCReg; + // Constants Related to the number of registers const int NumIntArchRegs = 32; @@ -64,6 +67,7 @@ const int NumInternalProcRegs = 0; const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; +const int NumCCRegs = 0; const int NumMiscRegs = NUM_MISCREGS; // Semantically meaningful register indices @@ -85,7 +89,8 @@ const int SyscallSuccessReg = 3; // These help enumerate all the registers for dependence tracking. const int FP_Reg_Base = NumIntRegs; -const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs; +const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; +const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; typedef union { -- cgit v1.2.3