From 5de8ca95506a5f15bfbfdd2ca9babd282a882d1f Mon Sep 17 00:00:00 2001 From: Robert Date: Tue, 13 Mar 2018 14:29:00 +0100 Subject: arch-riscv: enable rudimentary fs simulation These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/riscv/SConscript | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/riscv/SConscript') diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript index 4655057e5..2ddba722b 100644 --- a/src/arch/riscv/SConscript +++ b/src/arch/riscv/SConscript @@ -57,10 +57,13 @@ if env['TARGET_ISA'] == 'riscv': Source('stacktrace.cc') Source('tlb.cc') Source('system.cc') + Source('utility.cc') Source('linux/process.cc') Source('linux/linux.cc') + Source('bare_metal/system.cc') + SimObject('RiscvInterrupts.py') SimObject('RiscvISA.py') SimObject('RiscvTLB.py') -- cgit v1.2.3