From 4ae8d1c0ed18f351b52f421553b28fe109f87665 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 29 Jan 2020 16:49:40 -0800 Subject: arch,sim: Merge initCPU into the ISA System classes. Those classes are already ISA specific, so we can just move initCPU's contents there and take it out of utility.hh, utility.cc, and the base System's initState. Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/riscv/bare_metal/system.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/arch/riscv/bare_metal/system.cc') diff --git a/src/arch/riscv/bare_metal/system.cc b/src/arch/riscv/bare_metal/system.cc index 44e14e5ce..8d4ea414d 100644 --- a/src/arch/riscv/bare_metal/system.cc +++ b/src/arch/riscv/bare_metal/system.cc @@ -30,6 +30,7 @@ #include "arch/riscv/bare_metal/system.hh" +#include "arch/riscv/faults.hh" #include "base/loader/object_file.hh" BareMetalRiscvSystem::BareMetalRiscvSystem(Params *p) @@ -54,6 +55,11 @@ BareMetalRiscvSystem::initState() // Call the initialisation of the super class RiscvSystem::initState(); + for (auto *tc: threadContexts) { + RiscvISA::Reset().invoke(tc); + tc->activate(); + } + // load program sections into memory if (!bootloader->buildImage().write(physProxy)) { warn("could not load sections to memory"); -- cgit v1.2.3