From 68b6f9c8a1819fdeee737cf369cc6a499b505a6c Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Thu, 13 Jul 2017 14:24:06 -0400 Subject: riscv: Fix bugs with RISC-V decoder and detailed CPUs This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch. [Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.] Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power Maintainer: Alec Roelke --- src/arch/riscv/faults.hh | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/arch/riscv/faults.hh') diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh index d0d7988c5..1e33b648f 100644 --- a/src/arch/riscv/faults.hh +++ b/src/arch/riscv/faults.hh @@ -116,6 +116,19 @@ class UnknownInstFault : public RiscvFault invoke_se(ThreadContext *tc, const StaticInstPtr &inst); }; +class IllegalInstFault : public RiscvFault +{ + private: + const std::string reason; + public: + IllegalInstFault(std::string r) + : RiscvFault("Illegal instruction", INST_ILLEGAL, SOFTWARE), + reason(r) + {} + + void invoke_se(ThreadContext *tc, const StaticInstPtr &inst); +}; + class UnimplementedFault : public RiscvFault { private: -- cgit v1.2.3