From 3f31abfbc84734dab86734c72bdca778575c26e5 Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Fri, 10 Nov 2017 12:23:43 -0500 Subject: arch-riscv: Remove static parts of AMOs out of ISA This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black Maintainer: Alec Roelke --- src/arch/riscv/insts/SConscript | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/riscv/insts/SConscript') diff --git a/src/arch/riscv/insts/SConscript b/src/arch/riscv/insts/SConscript index 8bedc7b73..ad504e2f8 100644 --- a/src/arch/riscv/insts/SConscript +++ b/src/arch/riscv/insts/SConscript @@ -1,6 +1,7 @@ Import('*') if env['TARGET_ISA'] == 'riscv': + Source('amo.cc') Source('mem.cc') Source('standard.cc') Source('static_inst.cc') \ No newline at end of file -- cgit v1.2.3