From 719ddf73afa62735881ac68acf681abe1bf3bd17 Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Tue, 7 Nov 2017 15:19:56 -0500 Subject: arch-riscv: Move parts of mem insts out of ISA This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Reviewed-on: https://gem5-review.googlesource.com/6024 Reviewed-by: Gabe Black Maintainer: Alec Roelke --- src/arch/riscv/insts/SConscript | 1 + src/arch/riscv/insts/bitfields.hh | 3 ++ src/arch/riscv/insts/mem.cc | 65 +++++++++++++++++++++++++++++++++ src/arch/riscv/insts/mem.hh | 75 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 144 insertions(+) create mode 100644 src/arch/riscv/insts/mem.cc create mode 100644 src/arch/riscv/insts/mem.hh (limited to 'src/arch/riscv/insts') diff --git a/src/arch/riscv/insts/SConscript b/src/arch/riscv/insts/SConscript index fe9028029..8bedc7b73 100644 --- a/src/arch/riscv/insts/SConscript +++ b/src/arch/riscv/insts/SConscript @@ -1,5 +1,6 @@ Import('*') if env['TARGET_ISA'] == 'riscv': + Source('mem.cc') Source('standard.cc') Source('static_inst.cc') \ No newline at end of file diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh index d6648227e..eac070e7f 100644 --- a/src/arch/riscv/insts/bitfields.hh +++ b/src/arch/riscv/insts/bitfields.hh @@ -5,6 +5,9 @@ #define CSRIMM bits(machInst, 19, 15) #define FUNCT12 bits(machInst, 31, 20) +#define IMM5 bits(machInst, 11, 7) +#define IMM7 bits(machInst, 31, 25) +#define IMMSIGN bits(machInst, 31) #define OPCODE bits(machInst, 6, 0) #endif // __ARCH_RISCV_BITFIELDS_HH__ \ No newline at end of file diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc new file mode 100644 index 000000000..862700b0c --- /dev/null +++ b/src/arch/riscv/insts/mem.cc @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2015 RISC-V Foundation + * Copyright (c) 2017 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#include "arch/riscv/insts/mem.hh" + +#include +#include + +#include "arch/riscv/insts/bitfields.hh" +#include "arch/riscv/insts/static_inst.hh" +#include "arch/riscv/utility.hh" +#include "cpu/static_inst.hh" + +using namespace std; + +namespace RiscvISA +{ + +string +Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + stringstream ss; + ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << + offset << '(' << registerName(_srcRegIdx[0]) << ')'; + return ss.str(); +} + +string +Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + stringstream ss; + ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " << + offset << '(' << registerName(_srcRegIdx[0]) << ')'; + return ss.str(); +} + +} diff --git a/src/arch/riscv/insts/mem.hh b/src/arch/riscv/insts/mem.hh new file mode 100644 index 000000000..514d4d6e1 --- /dev/null +++ b/src/arch/riscv/insts/mem.hh @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015 RISC-V Foundation + * Copyright (c) 2017 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#ifndef __ARCH_RISCV_INST_MEM_HH__ +#define __ARCH_RISCV_INST_MEM_HH__ + +#include + +#include "arch/riscv/insts/static_inst.hh" +#include "cpu/exec_context.hh" +#include "cpu/static_inst.hh" + +namespace RiscvISA +{ + +class MemInst : public RiscvStaticInst +{ + protected: + int64_t offset; + Request::Flags memAccessFlags; + + MemInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) + : RiscvStaticInst(mnem, _machInst, __opClass), offset(0) + {} +}; + +class Load : public MemInst +{ + protected: + using MemInst::MemInst; + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; +}; + +class Store : public MemInst +{ + protected: + using MemInst::MemInst; + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; +}; + +} + +#endif // __ARCH_RISCV_INST_MEM_HH__ -- cgit v1.2.3