From ce00e6042d996a9255960917f99009d9826b3885 Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Sun, 10 Dec 2017 14:15:51 -0500 Subject: arch-riscv: Update CSR implementations This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers based on privilege will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Reviewed-on: https://gem5-review.googlesource.com/7441 Reviewed-by: Gabe Black Maintainer: Alec Roelke --- src/arch/riscv/insts/standard.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/riscv/insts') diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index 60cf4fc2b..9354a542f 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -60,12 +60,12 @@ CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "; if (_numSrcRegs > 0) ss << registerName(_srcRegIdx[0]) << ", "; - auto name = MiscRegNames.find(csr); - if (name != MiscRegNames.end()) - ss << name->second; + auto data = CSRData.find(csr); + if (data != CSRData.end()) + ss << data->second.name; else ss << "?? (" << hex << "0x" << csr << ")"; return ss.str(); } -} \ No newline at end of file +} -- cgit v1.2.3