From 63d4005a29dea37e0219444a3de2cdb25289fdfb Mon Sep 17 00:00:00 2001
From: Alec Roelke <ar4jc@virginia.edu>
Date: Thu, 15 Jun 2017 15:33:25 -0400
Subject: arch-riscv: Restructure ISA description

This patch restructures the RISC-V ISA description to use fewer classes
and improve its ability to be extended with nonstandard extensions in
the future. It also cleans up the disassembly for some of the CSR and
system instructions by removing source and destination registers for
instructions that don't have any.

[Fix class UImmOp to have an "imm" member rather than "uimm".]
[Update disassembly generation for new RegId class.]

Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9
Reviewed-on: https://gem5-review.googlesource.com/3800
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
---
 src/arch/riscv/isa/decoder.isa | 43 +++++++++++++++++++++---------------------
 1 file changed, 22 insertions(+), 21 deletions(-)

(limited to 'src/arch/riscv/isa/decoder.isa')

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 2b23c1fe4..8056d9615 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -467,7 +467,7 @@ decode OPCODE default Unknown::unknown() {
         }
     }
 
-    format FPR4Op {
+    format FPROp {
         0x43: decode FUNCT2 {
             0x0: fmadd_s({{
                 uint32_t temp;
@@ -680,10 +680,8 @@ decode OPCODE default Unknown::unknown() {
                 }
             }}, FloatMultOp);
         }
-    }
 
-    0x53: decode FUNCT7 {
-        format FPROp {
+        0x53: decode FUNCT7 {
             0x0: fadd_s({{
                 uint32_t temp;
                 float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
@@ -1274,8 +1272,9 @@ decode OPCODE default Unknown::unknown() {
             }}, FloatCvtOp);
         }
     }
+
     0x63: decode FUNCT3 {
-        format SBOp {
+        format BOp {
             0x0: beq({{
                 if (Rs1 == Rs2) {
                     NPC = PC + imm;
@@ -1328,13 +1327,13 @@ decode OPCODE default Unknown::unknown() {
         }}, IsIndirectControl, IsUncondControl, IsCall);
     }
 
-    0x6f: UJOp::jal({{
+    0x6f: JOp::jal({{
         Rd = NPC;
         NPC = PC + imm;
     }}, IsDirectControl, IsUncondControl, IsCall);
 
     0x73: decode FUNCT3 {
-        format IOp {
+        format SystemOp {
             0x0: decode FUNCT12 {
                 0x0: ecall({{
                     fault = std::make_shared<SyscallFault>();
@@ -1346,36 +1345,38 @@ decode OPCODE default Unknown::unknown() {
                     fault = std::make_shared<UnimplementedFault>("eret");
                 }}, No_OpClass);
             }
+        }
+        format CSROp {
             0x1: csrrw({{
-                Rd = xc->readMiscReg(FUNCT12);
-                xc->setMiscReg(FUNCT12, Rs1);
+                Rd = xc->readMiscReg(csr);
+                xc->setMiscReg(csr, Rs1);
             }}, IsNonSpeculative, No_OpClass);
             0x2: csrrs({{
-                Rd = xc->readMiscReg(FUNCT12);
+                Rd = xc->readMiscReg(csr);
                 if (Rs1 != 0) {
-                    xc->setMiscReg(FUNCT12, Rd | Rs1);
+                    xc->setMiscReg(csr, Rd | Rs1);
                 }
             }}, IsNonSpeculative, No_OpClass);
             0x3: csrrc({{
-                Rd = xc->readMiscReg(FUNCT12);
+                Rd = xc->readMiscReg(csr);
                 if (Rs1 != 0) {
-                    xc->setMiscReg(FUNCT12, Rd & ~Rs1);
+                    xc->setMiscReg(csr, Rd & ~Rs1);
                 }
             }}, IsNonSpeculative, No_OpClass);
             0x5: csrrwi({{
-                Rd = xc->readMiscReg(FUNCT12);
-                xc->setMiscReg(FUNCT12, ZIMM);
+                Rd = xc->readMiscReg(csr);
+                xc->setMiscReg(csr, uimm);
             }}, IsNonSpeculative, No_OpClass);
             0x6: csrrsi({{
-                Rd = xc->readMiscReg(FUNCT12);
-                if (ZIMM != 0) {
-                    xc->setMiscReg(FUNCT12, Rd | ZIMM);
+                Rd = xc->readMiscReg(csr);
+                if (uimm != 0) {
+                    xc->setMiscReg(csr, Rd | uimm);
                 }
             }}, IsNonSpeculative, No_OpClass);
             0x7: csrrci({{
-                Rd = xc->readMiscReg(FUNCT12);
-                if (ZIMM != 0) {
-                    xc->setMiscReg(FUNCT12, Rd & ~ZIMM);
+                Rd = xc->readMiscReg(csr);
+                if (uimm != 0) {
+                    xc->setMiscReg(csr, Rd & ~uimm);
                 }
             }}, IsNonSpeculative, No_OpClass);
         }
-- 
cgit v1.2.3