From b47b123b32d8125ed0e797f4ae8104f69cce1df7 Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Fri, 13 Jul 2018 10:48:01 -0400 Subject: arch-riscv: Add interrupt handling Implement the Interrupts SimObject for RISC-V. This basically just handles setting and getting the values of the interrupt-pending and interrupt-enable CSRs according to the privileged ISA reference chapter 3.1.14. Note that it does NOT implement the PLIC as defined in chapter 7, as that is used for handling external interrupts which are defined based on peripherals that are available. Change-Id: Ia1321430f870ff5a3950217266fde0511332485b Reviewed-on: https://gem5-review.googlesource.com/c/14377 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/riscv/isa/formats/standard.isa | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/arch/riscv/isa/formats/standard.isa') diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index e9539fe52..b2f8ee4bf 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -256,11 +256,25 @@ def template CSRExecute {{ } else { DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, CSRData.at(csr).name); + INTERRUPT oldinterrupt = olddata; + INTERRUPT newinterrupt = data; switch (csr) { case CSR_FCSR: xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0)); xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5)); break; + case CSR_MIP: case CSR_MIE: + if (oldinterrupt.mei == newinterrupt.mei && + oldinterrupt.mti == newinterrupt.mti && + oldinterrupt.msi == newinterrupt.msi) { + xc->setMiscReg(CSRData.at(csr).physIndex,data); + } else { + std::string error = "Interrupt m bits are " + "read-only\n"; + fault = make_shared(error, + machInst); + } + break; default: xc->setMiscReg(CSRData.at(csr).physIndex, data); break; -- cgit v1.2.3