From 1229b3b62303e00693cfb052fca6e4f7879cf0af Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Wed, 30 Nov 2016 17:10:28 -0500 Subject: riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power --- src/arch/riscv/isa/includes.isa | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch/riscv/isa/includes.isa') diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index 197133d25..c830f9085 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -68,12 +68,14 @@ using namespace RiscvISA; }}; output exec {{ +#include #include #include #include "arch/generic/memhelpers.hh" #include "arch/riscv/faults.hh" #include "arch/riscv/registers.hh" +#include "arch/riscv/utility.hh" #include "base/condcodes.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" -- cgit v1.2.3