From 63d4005a29dea37e0219444a3de2cdb25289fdfb Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Thu, 15 Jun 2017 15:33:25 -0400 Subject: arch-riscv: Restructure ISA description This patch restructures the RISC-V ISA description to use fewer classes and improve its ability to be extended with nonstandard extensions in the future. It also cleans up the disassembly for some of the CSR and system instructions by removing source and destination registers for instructions that don't have any. [Fix class UImmOp to have an "imm" member rather than "uimm".] [Update disassembly generation for new RegId class.] Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9 Reviewed-on: https://gem5-review.googlesource.com/3800 Maintainer: Alec Roelke Reviewed-by: Jason Lowe-Power --- src/arch/riscv/isa/includes.isa | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/riscv/isa/includes.isa') diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index c830f9085..443db6786 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -71,6 +71,7 @@ output exec {{ #include #include #include +#include #include "arch/generic/memhelpers.hh" #include "arch/riscv/faults.hh" -- cgit v1.2.3