From eb02066b31c85d22c67d1ead61048c196653ba1f Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Tue, 7 Nov 2017 14:15:41 -0500 Subject: arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power Maintainer: Alec Roelke --- src/arch/riscv/isa/includes.isa | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/riscv/isa/includes.isa') diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index 48f2b1957..dfd0f37b4 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -42,6 +42,7 @@ output header {{ #include #include +#include "arch/riscv/insts/standard.hh" #include "arch/riscv/insts/static_inst.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" -- cgit v1.2.3