From 126c0360e2efd9588f38128bad94c7fa82c79f25 Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Wed, 30 Nov 2016 17:10:28 -0500 Subject: riscv: [Patch 5/5] Added missing support for timing CPU models Last of five patches adding RISC-V to GEM5. This patch adds support for timing, minor, and detailed CPU models that was missing in the last four, which basically consists of handling timing-mode memory accesses and telling the minor and detailed models what a no-op instruction should be (addi zero, zero, 0). Patches 1-4 introduced RISC-V and implemented the base instruction set, RV64I, and added the multiply, floating point, and atomic memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] [Fixed some style errors in locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power --- src/arch/riscv/isa_traits.hh | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch/riscv/isa_traits.hh') diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh index a794a1889..f7a2c8762 100644 --- a/src/arch/riscv/isa_traits.hh +++ b/src/arch/riscv/isa_traits.hh @@ -63,6 +63,8 @@ using namespace LittleEndianGuest; const Addr PageShift = 12; const Addr PageBytes = ULL(1) << PageShift; +const ExtMachInst NoopMachInst = 0x00000013; + // Memory accesses can not be unaligned const bool HasUnalignedMemAcc = false; -- cgit v1.2.3