From a8f1f9811c3fdb1cf59f6d37540ad40e4699561f Mon Sep 17 00:00:00 2001 From: Alec Roelke Date: Tue, 21 Mar 2017 12:58:25 -0400 Subject: riscv: fix Linux problems with LR and SC ops Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions. Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke Reviewed-by: Jason Lowe-Power --- src/arch/riscv/locked_mem.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 src/arch/riscv/locked_mem.cc (limited to 'src/arch/riscv/locked_mem.cc') diff --git a/src/arch/riscv/locked_mem.cc b/src/arch/riscv/locked_mem.cc new file mode 100644 index 000000000..3c8dbe948 --- /dev/null +++ b/src/arch/riscv/locked_mem.cc @@ -0,0 +1,12 @@ +#include "arch/riscv/locked_mem.hh" + +#include + +#include "base/types.hh" + +namespace RiscvISA +{ + +std::stack locked_addrs; + +} -- cgit v1.2.3