From 0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 12 Oct 2018 23:39:36 -0700 Subject: arch: Make the ISA register types aliases for the global types. The ISA specific types can thus be phased out. Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60 Reviewed-on: https://gem5-review.googlesource.com/c/13623 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/riscv/registers.hh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/riscv/registers.hh') diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index bd95cf821..75f74ef2d 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -63,11 +63,11 @@ using RiscvISAInst::MaxInstSrcRegs; using RiscvISAInst::MaxInstDestRegs; const int MaxMiscDestRegs = 1; -typedef uint64_t IntReg; -typedef uint64_t FloatRegBits; -typedef double FloatReg; +typedef RegVal IntReg; +typedef RegVal FloatRegBits; +typedef FloatRegVal FloatReg; typedef uint8_t CCReg; // Not applicable to Riscv -typedef uint64_t MiscReg; +typedef RegVal MiscReg; // dummy typedefs since we don't have vector regs const unsigned NumVecElemPerVecReg = 2; -- cgit v1.2.3