From a119a963240a35ab66a5baee3f77cfcd99c6bbbb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 21 Nov 2018 16:20:57 -0800 Subject: cpu, arch: Replace the CCReg type with RegVal. Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/arch/riscv/registers.hh | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index e2d1d154b..c2e1fd2b5 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -64,8 +64,6 @@ using RiscvISAInst::MaxInstSrcRegs; using RiscvISAInst::MaxInstDestRegs; const int MaxMiscDestRegs = 1; -typedef uint8_t CCReg; // Not applicable to Riscv - // Not applicable to RISC-V using VecElem = ::DummyVecElem; using VecReg = ::DummyVecReg; -- cgit v1.2.3