From 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Jul 2009 23:02:20 -0700
Subject: Registers: Add an ISA object which replaces the MiscRegFile. This
object encapsulates (or will eventually) the identity and characteristics of
the ISA in the CPU.
---
src/arch/sparc/SConscript | 1 +
1 file changed, 1 insertion(+)
(limited to 'src/arch/sparc/SConscript')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 940cf2076..eb0d21598 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -36,6 +36,7 @@ if env['TARGET_ISA'] == 'sparc':
Source('faults.cc')
Source('floatregfile.cc')
Source('intregfile.cc')
+ Source('isa.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
Source('regfile.cc')
--
cgit v1.2.3
From 0cb180ea0dcece9157ad71b4136d557c2dbcf209 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Jul 2009 23:02:20 -0700
Subject: Registers: Eliminate the ISA defined floating point register file.
---
src/arch/sparc/SConscript | 1 -
1 file changed, 1 deletion(-)
(limited to 'src/arch/sparc/SConscript')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index eb0d21598..2b10951d9 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -34,7 +34,6 @@ Import('*')
if env['TARGET_ISA'] == 'sparc':
Source('asi.cc')
Source('faults.cc')
- Source('floatregfile.cc')
Source('intregfile.cc')
Source('isa.cc')
Source('miscregfile.cc')
--
cgit v1.2.3
From a480ba00b96f4c2e872f5a01bfa1782500f1066e Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Jul 2009 23:02:20 -0700
Subject: Registers: Eliminate the ISA defined integer register file.
---
src/arch/sparc/SConscript | 1 -
1 file changed, 1 deletion(-)
(limited to 'src/arch/sparc/SConscript')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 2b10951d9..cfc03b718 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -34,7 +34,6 @@ Import('*')
if env['TARGET_ISA'] == 'sparc':
Source('asi.cc')
Source('faults.cc')
- Source('intregfile.cc')
Source('isa.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
--
cgit v1.2.3
From b398b8ff1ba7e181e010afd6219074cf6f683820 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 8 Jul 2009 23:02:21 -0700
Subject: Registers: Add a registers.hh file as an ISA switched header. This
file is for register indices, Num* constants, and register types. copyRegs
and copyMiscRegs were moved to utility.hh and utility.cc.
--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
---
src/arch/sparc/SConscript | 1 -
1 file changed, 1 deletion(-)
(limited to 'src/arch/sparc/SConscript')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index cfc03b718..5dcadc143 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -37,7 +37,6 @@ if env['TARGET_ISA'] == 'sparc':
Source('isa.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
- Source('regfile.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
Source('utility.cc')
--
cgit v1.2.3
From 60d47aa5f9018bf29651ec33ae1f20793fcdc4eb Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 9 Jul 2009 20:28:50 -0700
Subject: SPARC: Fold the MiscRegFile all the way into the ISA object.
---
src/arch/sparc/SConscript | 1 -
1 file changed, 1 deletion(-)
(limited to 'src/arch/sparc/SConscript')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 5dcadc143..86ccaa010 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -35,7 +35,6 @@ if env['TARGET_ISA'] == 'sparc':
Source('asi.cc')
Source('faults.cc')
Source('isa.cc')
- Source('miscregfile.cc')
Source('pagetable.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
--
cgit v1.2.3