From 3e8e813218e7779a41bc12caae33db5e239506c9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 19 Jul 2009 23:54:56 -0700 Subject: CPU: Separate out native trace into ISA (in)dependent code and SimObjects. --HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py --- src/arch/sparc/SConscript | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/sparc/SConscript') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 86ccaa010..b59e9ea7a 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -35,11 +35,14 @@ if env['TARGET_ISA'] == 'sparc': Source('asi.cc') Source('faults.cc') Source('isa.cc') + Source('nativetrace.cc') Source('pagetable.cc') Source('remote_gdb.cc') Source('tlb.cc') Source('utility.cc') + SimObject('SparcNativeTrace.py') + SimObject('SparcTLB.py') TraceFlag('Sparc', "Generic SPARC ISA stuff") TraceFlag('RegisterWindows', "Register window manipulation") -- cgit v1.2.3