From ecbb8debf672ee1463115319a24384eeb6b98ee3 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 6 Dec 2006 14:29:10 -0500 Subject: Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28 --- src/arch/sparc/asi.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/arch/sparc/asi.cc') diff --git a/src/arch/sparc/asi.cc b/src/arch/sparc/asi.cc index 14e581e43..c8f2c1366 100644 --- a/src/arch/sparc/asi.cc +++ b/src/arch/sparc/asi.cc @@ -104,7 +104,7 @@ namespace SparcISA (asi == ASI_BLK_SL); } - bool AsiNucleus(ASI asi) + bool AsiIsNucleus(ASI asi) { return (asi == ASI_N) || @@ -259,6 +259,7 @@ namespace SparcISA bool AsiIsMmu(ASI asi) { return asi == ASI_MMU || + asi == ASI_LSU_CONTROL_REG || (asi >= ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 && asi <= ASI_IMMU_CTXT_ZERO_CONFIG) || (asi >= ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 && -- cgit v1.2.3