From 4301e4cd08018eb56b4f196afcce9a8311f390b4 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 23 Jan 2007 15:50:03 -0500 Subject: use pstate.am to mask off PC/NPC where it needs to +be check writability of tlb cache entry before using update tagaccess in places I forgot to move the tlb privileged test up since it is higher priority src/arch/sparc/faults.cc: save only 32 bits of PC/NPC if Pstate.am is set src/arch/sparc/isa/decoder.isa: return only 32 bits of PC/NPC if Pstate.am is set increment cleanwin correctly src/arch/sparc/tlb.cc: check writability of cache entry update tagaccess in a few more places move the privileged test up since it is higher priority src/cpu/exetrace.cc: mask off upper bits of pc if pstate.am is set before comparing to legion --HG-- extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c --- src/arch/sparc/faults.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/arch/sparc/faults.cc') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index b465e52d2..825ff40f6 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -312,6 +312,11 @@ void doREDFault(ThreadContext *tc, TrapType tt) TL++; + if (bits(PSTATE, 3,3)) { + PC &= mask(32); + NPC &= mask(32); + } + //set TSTATE.gl to gl replaceBits(TSTATE, 42, 40, GL); //set TSTATE.ccr to ccr @@ -390,6 +395,11 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) MiscReg PC = tc->readPC(); MiscReg NPC = tc->readNextPC(); + if (bits(PSTATE, 3,3)) { + PC &= mask(32); + NPC &= mask(32); + } + //Increment the trap level TL++; tc->setMiscReg(MISCREG_TL, TL); -- cgit v1.2.3