From ed22eb781dc7714c1b2ca17cf17824917e38319c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 7 Dec 2006 18:50:33 -0500 Subject: get legion/m5 to first tlb miss fault src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca --- src/arch/sparc/faults.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/arch/sparc/faults.cc') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 9a29f24d5..78b2b4b76 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -528,7 +528,7 @@ void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscRe void SparcFaultBase::invoke(ThreadContext * tc) { - panic("Invoking a second fault!\n"); + //panic("Invoking a second fault!\n"); FaultBase::invoke(tc); countStat()++; @@ -561,6 +561,7 @@ void SparcFaultBase::invoke(ThreadContext * tc) } else if(TL == MaxTL) { + panic("Should go to error state here.. crap\n"); //Do error_state somehow? //Probably inject a WDR fault using the interrupt mechanism. //What should the PC and NPC be set to? -- cgit v1.2.3