From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001
From: Yasuko Eckert <yasuko.eckert@amd.com>
Date: Tue, 15 Oct 2013 14:22:44 -0400
Subject: cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
---
 src/arch/sparc/isa.hh | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/arch/sparc/isa.hh')

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 86092f3b5..e6f023bc0 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -206,6 +206,13 @@ class ISA : public SimObject
         return reg;
     }
 
+    // dummy
+    int
+    flattenCCIndex(int reg)
+    {
+        return reg;
+    }
+
     typedef SparcISAParams Params;
     const Params *params() const;
 
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