From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001
From: Nathanael Premillieu <nathanael.premillieu@arm.com>
Date: Wed, 5 Apr 2017 12:46:06 -0500
Subject: arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
---
 src/arch/sparc/isa/formats/integerop.isa | 4 ++--
 src/arch/sparc/isa/formats/mem/util.isa  | 4 ++--
 src/arch/sparc/isa/formats/priv.isa      | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/arch/sparc/isa/formats')

diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 355bbf393..585dfcced 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -155,7 +155,7 @@ output decoder {{
         IntOp::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) {
+            if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].regIdx == 0) {
                 printMnemonic(os, "mov");
                 printSrcReg(os, 1);
                 ccprintf(os, ", ");
@@ -170,7 +170,7 @@ output decoder {{
                 const SymbolTable *symbab) const
         {
             if (!std::strcmp(mnemonic, "or")) {
-                if (_numSrcRegs > 0 && _srcRegIdx[0] == 0) {
+                if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx == 0) {
                     if (imm == 0) {
                         printMnemonic(os, "clr");
                     } else {
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 0a07f55dd..9b3132e40 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -84,7 +84,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!store ? 0 : 1] != 0) {
+            if (_srcRegIdx[!store ? 0 : 1].regIdx != 0) {
                 printSrcReg(response, !store ? 0 : 1);
                 ccprintf(response, " + ");
             }
@@ -111,7 +111,7 @@ output decoder {{
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[");
-            if (_srcRegIdx[!save ? 0 : 1] != 0) {
+            if (_srcRegIdx[!save ? 0 : 1].regIdx != 0) {
                 printReg(response, _srcRegIdx[!save ? 0 : 1]);
                 ccprintf(response, " + ");
             }
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 24b553fe3..f5e1a0826 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -155,7 +155,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0] != 0) {
+            if (_srcRegIdx[0].regIdx != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
@@ -175,7 +175,7 @@ output decoder {{
             ccprintf(response, " ");
             // If the first reg is %g0, don't print it.
             // This improves readability
-            if (_srcRegIdx[0] != 0) {
+            if (_srcRegIdx[0].regIdx != 0) {
                 printSrcReg(response, 0);
                 ccprintf(response, ", ");
             }
-- 
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