From 8561c8366c7c9afd7e6b52b6e2385b3c1dde95a9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 25 Jan 2007 13:43:46 -0500 Subject: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back --HG-- extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4 --- src/arch/sparc/isa/formats/mem/blockmem.isa | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/arch/sparc/isa/formats') diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 32421a75f..c36fede2e 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -476,7 +476,6 @@ let {{ faultCode = '' return (header_output, decoder_output, exec_output, decode_block) - def doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags): addrCalcReg = 'EA = Rs1 + Rs2 + offset;' addrCalcImm = 'EA = Rs1 + imm + offset;' @@ -492,10 +491,11 @@ let {{ pcedCode = '' if (microPc == 1): flag_code = "flags[IsLastMicroOp] = true;" - pcedCode = matcher.sub("RdHigh", code) + pcedCode = "RdLow = uReg0;\n" + pcedCode += matcher.sub("RdHigh", code) else: flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" - pcedCode = matcher.sub("RdLow", code) + pcedCode = matcher.sub("uReg0", code) iop = InstObjParams(name, Name, 'TwinMem', pcedCode, opt_flags, {"ea_code": addrCalcReg, "fault_check": faultCode, "micro_pc": microPc, -- cgit v1.2.3