From f01d2efe8a106692fd83936d3c6d3565a001616c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Dec 2010 00:27:43 -0800 Subject: SPARC: Take advantage of new PCState syntax. --- src/arch/sparc/isa/operands.isa | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch/sparc/isa/operands.isa') diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index a72fd12b9..dfc71f419 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -129,7 +129,9 @@ def operands {{ #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), - 'PCS': ('PCState', 'udw', None, (None, None, 'IsControl'), 30), + 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), + 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), + 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), # Registers which are used explicitly in instructions 'R0': ('IntReg', 'udw', '0', None, 6), 'R1': ('IntReg', 'udw', '1', None, 7), -- cgit v1.2.3