From 12eb0343784f52994110df7e7fce4a0b639a6ec3 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Mon, 11 Jan 2016 05:52:20 -0500
Subject: scons: Enable -Wextra by default

Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
---
 src/arch/sparc/isa/decoder.isa | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/arch/sparc/isa')

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index befac53e6..492e1a00a 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -669,13 +669,13 @@ decode OP default Unknown::unknown()
                     }});
                     0x43: FpUnimpl::fmovq_fcc1();
                     0x45: fmovrslez({{
-                        if (Rs1 <= 0)
+                        if ((int64_t)Rs1 <= 0)
                             Frds = Frs2s;
                         else
                             Frds = Frds;
                     }});
                     0x46: fmovrdlez({{
-                        if (Rs1 <= 0)
+                        if ((int64_t)Rs1 <= 0)
                             Frd = Frs2;
                         else
                             Frd = Frd;
@@ -740,13 +740,13 @@ decode OP default Unknown::unknown()
                     }});
                     0x57: FpUnimpl::fcmpeq();
                     0x65: fmovrslz({{
-                        if (Rs1 < 0)
+                        if ((int64_t)Rs1 < 0)
                             Frds = Frs2s;
                         else
                             Frds = Frds;
                     }});
                     0x66: fmovrdlz({{
-                        if (Rs1 < 0)
+                        if ((int64_t)Rs1 < 0)
                             Frd = Frs2;
                         else
                             Frd = Frd;
@@ -792,26 +792,26 @@ decode OP default Unknown::unknown()
                     }});
                     0xC3: FpUnimpl::fmovq_fcc3();
                     0xC5: fmovrsgz({{
-                        if (Rs1 > 0)
+                        if ((int64_t)Rs1 > 0)
                             Frds = Frs2s;
                         else
                             Frds = Frds;
                     }});
                     0xC6: fmovrdgz({{
-                        if (Rs1 > 0)
+                        if ((int64_t)Rs1 > 0)
                             Frd = Frs2;
                         else
                             Frd = Frd;
                     }});
                     0xC7: FpUnimpl::fmovrqgz();
                     0xE5: fmovrsgez({{
-                        if (Rs1 >= 0)
+                        if ((int64_t)Rs1 >= 0)
                             Frds = Frs2s;
                         else
                             Frds = Frds;
                     }});
                     0xE6: fmovrdgez({{
-                        if (Rs1 >= 0)
+                        if ((int64_t)Rs1 >= 0)
                             Frd = Frs2;
                         else
                             Frd = Frd;
-- 
cgit v1.2.3