From 9d04510869fe66d59a168660925a8387c0fba1b8 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 10 Jan 2007 22:19:13 -0500 Subject: bug fixes to get us to 145m instructions src/arch/sparc/intregfile.cc: some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now src/arch/sparc/isa/decoder.isa: fix smul instruction to write Y correctly src/arch/sparc/miscregfile.cc: legion always returns du and dl set, so we need to emulate that for now at least --HG-- extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8 --- src/arch/sparc/isa/decoder.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index e2bebd987..2e1344a8f 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -184,7 +184,7 @@ decode OP default Unknown::unknown() }}); 0x0B: smul({{ Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; - Y = Rd.sdw; + Y = Rd.sdw<63:32>; }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 0x0D: udivx({{ -- cgit v1.2.3 From ecfd628ecd394f8e7df654ffc7c342d959e12e15 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 16 Jan 2007 19:06:05 -0500 Subject: Modify ISA and staticInst to support a IsFirstMicroOp flag Increment instruction count on first micro-op instead of last src/arch/sparc/isa/decoder.isa: Implement a twin load for ASI_LDTX_P(0xe2) src/arch/sparc/isa/formats/mem/blockmem.isa: set the new flag IsFirstMicroOp when needed src/cpu/simple/atomic.cc: Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion) src/cpu/static_inst.hh: Add IsFirstMicroop flag to static insts --HG-- extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc --- src/arch/sparc/isa/decoder.isa | 3 +++ src/arch/sparc/isa/formats/mem/blockmem.isa | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 2e1344a8f..bd1a44342 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1079,6 +1079,9 @@ decode OP default Unknown::unknown() //ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + //ASI_LDTX_P + 0xE2: TwinLoad::ldtx_p( + {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); default: ldtwa({{ uint64_t val = Mem.udw; RdLow = val<31:0>; diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 5d05dad03..32421a75f 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -451,6 +451,8 @@ let {{ flag_code = '' if (microPc == 7): flag_code = "flags[IsLastMicroOp] = true;" + elif (microPc == 0): + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) @@ -492,7 +494,7 @@ let {{ flag_code = "flags[IsLastMicroOp] = true;" pcedCode = matcher.sub("RdHigh", code) else: - flag_code = "flags[IsDelayedCommit] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" pcedCode = matcher.sub("RdLow", code) iop = InstObjParams(name, Name, 'TwinMem', pcedCode, opt_flags, {"ea_code": addrCalcReg, -- cgit v1.2.3 From 6e0f1c6062e795201e3ffe1d8a8821e96a6a4b97 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 20 Jan 2007 12:34:00 -0500 Subject: Spill and Fill handlers are actually n*4 + the start address --HG-- extra : convert_revision : a42f01a84e4b7ba9e6029df50e1612d410a8ba22 --- src/arch/sparc/isa/decoder.isa | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index bd1a44342..2c1b92799 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -471,9 +471,9 @@ decode OP default Unknown::unknown() if(NWindows - 2 - Cansave == 0) { if(Otherwin) - fault = new SpillNOther(Wstate<5:3>); + fault = new SpillNOther(4*Wstate<5:3>); else - fault = new SpillNNormal(Wstate<2:0>); + fault = new SpillNNormal(4*Wstate<2:0>); } }}); 0x2C: decode MOVCC3 @@ -893,9 +893,9 @@ decode OP default Unknown::unknown() if(Canrestore == 0) { if(Otherwin) - fault = new FillNOther(Wstate<5:3>); + fault = new FillNOther(4*Wstate<5:3>); else - fault = new FillNNormal(Wstate<2:0>); + fault = new FillNNormal(4*Wstate<2:0>); } else { @@ -949,9 +949,9 @@ decode OP default Unknown::unknown() if(Cansave == 0) { if(Otherwin) - fault = new SpillNOther(Wstate<5:3>); + fault = new SpillNOther(4*Wstate<5:3>); else - fault = new SpillNNormal(Wstate<2:0>); + fault = new SpillNNormal(4*Wstate<2:0>); //Cwp = (Cwp + 2) % NWindows; } else if(Cleanwin - Canrestore == 0) @@ -975,9 +975,9 @@ decode OP default Unknown::unknown() if(Canrestore == 0) { if(Otherwin) - fault = new FillNOther(Wstate<5:3>); + fault = new FillNOther(4*Wstate<5:3>); else - fault = new FillNNormal(Wstate<2:0>); + fault = new FillNNormal(4*Wstate<2:0>); } else { -- cgit v1.2.3 From 95e4a51c6cf89c5269c758d40dd7952d43d2a3a7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 20 Jan 2007 23:09:28 -0500 Subject: fix flushw implementation --HG-- extra : convert_revision : 136b2bddc7cb70cde30e930ad3a13bd56c7162e1 --- src/arch/sparc/isa/decoder.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 2c1b92799..dafdc96f6 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -468,7 +468,7 @@ decode OP default Unknown::unknown() //0x11-0x1F should cause an illegal instruction exception } 0x2B: BasicOperate::flushw({{ - if(NWindows - 2 - Cansave == 0) + if(NWindows - 2 - Cansave != 0) { if(Otherwin) fault = new SpillNOther(4*Wstate<5:3>); -- cgit v1.2.3 From 5f662d451ee8311c0f42eaf6ed6415b4d0f0f473 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 22 Jan 2007 21:55:43 -0500 Subject: clean up fault code a little bit simplify and make complete some asi checks implement all the twin asis and remove panic checks on their use soft int is supported, so we don't need to print writes to it src/arch/sparc/asi.cc: make AsiIsLittle() be all the little asis. Speed up AsiIsTwin() a bit src/arch/sparc/faults.cc: clean up the do*Fault code.... Make it work like legion, in particular pstate.priv is left alone, not set to 0 like the spec says src/arch/sparc/isa/decoder.isa: implement some more twin ASIs src/arch/sparc/tlb.cc: All the twin asis are implemented, no need to say their not supported anymore src/arch/sparc/ua2005.cc: softint is supported now, no more need to --HG-- extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b --- src/arch/sparc/isa/decoder.isa | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index dafdc96f6..175866eba 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1061,6 +1061,12 @@ decode OP default Unknown::unknown() 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 0x13: decode EXT_ASI { + //ASI_LDTD_AIUP + 0x22: TwinLoad::ldtx_aiup( + {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + //ASI_LDTD_AIUS + 0x23: TwinLoad::ldtx_aius( + {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); //ASI_QUAD_LDD 0x24: TwinLoad::ldtx_quad_ldd( {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); @@ -1082,6 +1088,9 @@ decode OP default Unknown::unknown() //ASI_LDTX_P 0xE2: TwinLoad::ldtx_p( {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + //ASI_LDTX_S + 0xE3: TwinLoad::ldtx_s( + {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); default: ldtwa({{ uint64_t val = Mem.udw; RdLow = val<31:0>; -- cgit v1.2.3