From 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 1 Nov 2006 16:44:45 -0500
Subject: Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing
 register file functions to not take faults

--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
---
 src/arch/sparc/isa/decoder.isa | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/arch/sparc/isa')

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index a64ff09bb..a5f43367d 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -353,14 +353,14 @@ decode OP default Unknown::unknown()
                     0x1: Nop::membar({{/*stuff*/}});
                 }
                 default: rdasr({{
-                Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
+                Rd = xc->readMiscRegWithEffect(RS1 + AsrStart);
                 }});
             }
             0x29: HPriv::rdhpr({{
-                Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
+                Rd = xc->readMiscRegWithEffect(RS1 + HprStart);
             }});
             0x2A: Priv::rdpr({{
-                Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
+                Rd = xc->readMiscRegWithEffect(RS1 + PrStart);
             }});
             0x2B: BasicOperate::flushw({{
                 if(NWindows - 2 - Cansave == 0)
-- 
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