From 5b557a314f4dbde6f029b3f75c211332ac360f3a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 11 Feb 2012 14:16:38 -0800 Subject: SPARC: Make PSTATE and HPSTATE a BitUnion. This gets rid of cryptic bits of code with lots of bit manipulation, and makes some comments redundant. --- src/arch/sparc/isa/base.isa | 4 ++-- src/arch/sparc/isa/decoder.isa | 16 ++++++++-------- src/arch/sparc/isa/formats/mem/util.isa | 8 ++++---- src/arch/sparc/isa/formats/priv.isa | 4 ++-- src/arch/sparc/isa/operands.isa | 9 ++++++--- 5 files changed, 22 insertions(+), 19 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index d38df1c25..3b3974cbf 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -567,8 +567,8 @@ output exec {{ checkFpEnableFault(%(CPU_exec_context)s *xc) { if (FullSystem) { - if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && - xc->readMiscReg(MISCREG_FPRS) & 0x4) { + PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE); + if (pstate.pef && xc->readMiscReg(MISCREG_FPRS) & 0x4) { return NoFault; } else { return new FpDisabled; diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index a05cb94f7..44d2643c6 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -139,7 +139,7 @@ decode OP default Unknown::unknown() } 0x1: BranchN::call(30, {{ IntReg midVal; - R15 = midVal = (Pstate<3:> ? (PC)<31:0> : PC); + R15 = midVal = (Pstate.am ? (PC)<31:0> : PC); NNPC = midVal + disp; }},None, None, IsIndirectControl, IsCall); 0x2: decode OP3 { @@ -327,7 +327,7 @@ decode OP default Unknown::unknown() 0x03: NoPriv::rdasi({{Rd = Asi;}}); 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 0x05: NoPriv::rdpc({{ - if (Pstate<3:>) + if (Pstate.am) Rd = (PC)<31:0>; else Rd = PC; @@ -356,7 +356,7 @@ decode OP default Unknown::unknown() 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 0x1A: Priv::rdstrand_sts_reg({{ - if (Pstate<2:> && !Hpstate<2:>) + if (Pstate.am && !Hpstate.hpriv) Rd = StrandStsReg<0:>; else Rd = StrandStsReg; @@ -479,7 +479,7 @@ decode OP default Unknown::unknown() 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); // 0x12 should cause an illegal instruction exception 0x13: NoPriv::wrgsr({{ - if (Fprs<2:> == 0 || Pstate<4:> == 0) + if (Fprs<2:> == 0 || Pstate.pef == 0) return new FpDisabled; Gsr = Rs1 ^ Rs2_or_imm13; }}); @@ -488,7 +488,7 @@ decode OP default Unknown::unknown() 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x18: NoPriv::wrstick({{ - if (!Hpstate<2:>) + if (!Hpstate.hpriv) return new IllegalInstruction; Stick = Rs1 ^ Rs2_or_imm13; }}); @@ -536,7 +536,7 @@ decode OP default Unknown::unknown() 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 0x07: Priv::wrprtl({{ - if (Pstate<2:> && !Hpstate<2:>) + if (Pstate.priv && !Hpstate.hpriv) Tl = std::min(Rs1 ^ Rs2_or_imm13, MaxPTL); else Tl = std::min(Rs1 ^ Rs2_or_imm13, MaxTL); @@ -550,7 +550,7 @@ decode OP default Unknown::unknown() 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); // 0x0F should cause an illegal instruction exception 0x10: Priv::wrprgl({{ - if (Pstate<2:> && !Hpstate<2:>) + if (Pstate.priv && !Hpstate.hpriv) Gl = std::min(Rs1 ^ Rs2_or_imm13, MaxPGL); else Gl = std::min(Rs1 ^ Rs2_or_imm13, MaxGL); @@ -997,7 +997,7 @@ decode OP default Unknown::unknown() if (target & 0x3) { fault = new MemAddressNotAligned; } else { - if (Pstate<3:>) + if (Pstate.am) Rd = (PC)<31:0>; else Rd = PC; diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index a77059181..ffce3063b 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -317,17 +317,17 @@ let {{ # are split into ones that are available in priv and hpriv, and # those that are only available in hpriv AlternateASIPrivFaultCheck = ''' - if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) && + if ((!Pstate.priv && !Hpstate.hpriv && !asiIsUnPriv((ASI)EXT_ASI)) || - (!bits(Hpstate,2,2) && asiIsHPriv((ASI)EXT_ASI))) + (!Hpstate.hpriv && asiIsHPriv((ASI)EXT_ASI))) fault = new PrivilegedAction; - else if (asiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) + else if (asiIsAsIfUser((ASI)EXT_ASI) && !Pstate.priv) fault = new PrivilegedAction; ''' TruncateEA = ''' if (!FullSystem) - EA = Pstate<3:> ? EA<31:0> : EA; + EA = Pstate.am ? EA<31:0> : EA; ''' }}; diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 56f1cdbd9..e3242aab8 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -264,7 +264,7 @@ let {{ }}; def format Priv(code, extraCond=true, checkTl=false, *opt_flags) {{ - checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCond + checkCode = "(%s) && !(Pstate.priv || Hpstate.hpriv)" % extraCond if checkTl != "false": tlCheck = "Tl == 0" else: @@ -289,7 +289,7 @@ def format NoPriv(code, checkTl=false, *opt_flags) {{ }}; def format HPriv(code, checkTl=false, *opt_flags) {{ - checkCode = "!Hpstate<2:2>" + checkCode = "!Hpstate.hpriv" if checkTl != "false": tlCheck = "Tl == 0" else: diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 425f6c317..32a39bbee 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -40,7 +40,10 @@ def operand_types {{ 'tudw' : 'Twin64_t', 'tuw' : 'Twin32_t', 'sf' : 'float', - 'df' : 'double' + 'df' : 'double', + + 'pstate' : 'PSTATE', + 'hpstate' : 'HPSTATE' }}; output header {{ @@ -167,7 +170,7 @@ def operands {{ 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), - 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), + 'Pstate': ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59), 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), @@ -183,7 +186,7 @@ def operands {{ 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), - 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), + 'Hpstate': ('ControlReg', 'hpstate', 'MISCREG_HPSTATE', None, 69), 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), -- cgit v1.2.3