From 3140dd88bc588ea51aadeb2dd58d33cc9a40883a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 14 Apr 2007 17:07:24 +0000 Subject: Make the fsr a serializing register. Other control registers probably need this as well. --HG-- extra : convert_revision : edd3f9a83cc2722b6e0eff0eff4a8e034b0f6ec6 --- src/arch/sparc/isa/operands.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 58d616a7a..110b37d15 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -187,7 +187,7 @@ def operands {{ 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), - 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), + 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), # Mem gets a large number so it's always last 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) -- cgit v1.2.3 From cea543576082ed860e8dae17519ace48e5b2c78a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 22 Apr 2007 17:43:45 +0000 Subject: Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used. --HG-- extra : convert_revision : ffeb4f874bd4430255064f6e8bcb135309932ff8 --- src/arch/sparc/isa/operands.isa | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 110b37d15..a627a2e6f 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -149,7 +149,8 @@ def operands {{ 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), - 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), +# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), + 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), -- cgit v1.2.3 From dc1c9e03007f084caabc995b41616603e0a004dc Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 8 May 2007 13:02:19 +0000 Subject: Add a hack to truncate addresses to 32 bits in SE. Paging should be changed to use the architecture's TLB, at which point this can be removed. --HG-- extra : convert_revision : 54f3c18e5aead727d0ac244ed00fd97d3ca8ad75 --- src/arch/sparc/isa/formats/mem/basicmem.isa | 6 ++++-- src/arch/sparc/isa/formats/mem/blockmem.isa | 6 ++++-- src/arch/sparc/isa/formats/mem/swap.isa | 8 ++++++-- src/arch/sparc/isa/formats/mem/util.isa | 12 +++++++++++- 4 files changed, 25 insertions(+), 7 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index 2f62c7bef..aa6c4cdea 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -57,10 +57,12 @@ let {{ addrCalcImm = 'EA = Rs1 + imm;' iop = InstObjParams(name, Name, 'Mem', {"code": code, "postacc_code" : postacc_code, - "fault_check": faultCode, "ea_code": addrCalcReg}, opt_flags) + "fault_check": faultCode, "ea_code": addrCalcReg, + "EA_trunc": TruncateEA}, opt_flags) iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', {"code": code, "postacc_code" : postacc_code, - "fault_check": faultCode, "ea_code": addrCalcImm}, opt_flags) + "fault_check": faultCode, "ea_code": addrCalcImm, + "EA_trunc": TruncateEA}, opt_flags) header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm) decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) decode_block = ROrImmDecode.subst(iop) diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index e19016bd0..ea74ef179 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -298,11 +298,13 @@ let {{ iop = InstObjParams(name, Name, 'BlockMem', {"code": pcedCode, "ea_code": addrCalcReg, "fault_check": faultCode, "micro_pc": microPc, - "set_flags": flag_code}, opt_flags) + "set_flags": flag_code, "EA_trunc" : TruncateEA}, + opt_flags) iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', {"code": pcedCode, "ea_code": addrCalcImm, "fault_check": faultCode, "micro_pc": microPc, - "set_flags": flag_code}, opt_flags) + "set_flags": flag_code, "EA_trunc" : TruncateEA}, + opt_flags) decoder_output += BlockMemMicroConstructor.subst(iop) decoder_output += BlockMemMicroConstructor.subst(iop_imm) exec_output += doDualSplitExecute( diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index b71542a2b..3814d1030 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -51,6 +51,7 @@ def template SwapExecute {{ } if(storeCond && fault == NoFault) { + %(EA_trunc)s fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, &mem_data); } @@ -91,6 +92,7 @@ def template SwapInitiateAcc {{ } if(fault == NoFault) { + %(EA_trunc)s fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, &mem_data); } @@ -157,12 +159,14 @@ let {{ addrCalcReg = 'EA = Rs1;' iop = InstObjParams(name, Name, 'Mem', {"code": code, "postacc_code" : postacc_code, - "fault_check": faultCode, "ea_code": addrCalcReg}, opt_flags) + "fault_check": faultCode, "ea_code": addrCalcReg, + "EA_trunc" : TruncateEA}, opt_flags) header_output = MemDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) microParams = {"code": code, "postacc_code" : postacc_code, - "ea_code" : addrCalcReg, "fault_check" : faultCode} + "ea_code" : addrCalcReg, "fault_check" : faultCode, + "EA_trunc" : TruncateEA} exec_output = doSplitExecute(execute, name, Name, asi, ["IsStoreConditional"], microParams); return (header_output, decoder_output, exec_output, decode_block) diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index dfe937371..38cde9a50 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -149,6 +149,7 @@ def template LoadExecute {{ %(fault_check)s; if(fault == NoFault) { + %(EA_trunc)s fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); } if(fault == NoFault) @@ -179,6 +180,7 @@ def template LoadInitiateAcc {{ %(fault_check)s; if(fault == NoFault) { + %(EA_trunc)s fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); } return fault; @@ -224,6 +226,7 @@ def template StoreExecute {{ } if(storeCond && fault == NoFault) { + %(EA_trunc)s fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, 0); } @@ -257,6 +260,7 @@ def template StoreInitiateAcc {{ } if(storeCond && fault == NoFault) { + %(EA_trunc)s fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, 0); } @@ -317,6 +321,11 @@ let {{ fault = new PrivilegedAction; ''' + TruncateEA = ''' +#if !FULL_SYSTEM + EA = Pstate<3:> ? EA<31:0> : EA; +#endif + ''' }}; //A simple function to generate the name of the macro op of a certain @@ -346,7 +355,8 @@ let {{ (eaRegCode, nameReg, NameReg), (eaImmCode, nameImm, NameImm)): microParams = {"code": code, "postacc_code" : postacc_code, - "ea_code": eaCode, "fault_check": faultCode} + "ea_code": eaCode, "fault_check": faultCode, + "EA_trunc" : TruncateEA} executeCode += doSplitExecute(execute, name, Name, asi, opt_flags, microParams) return executeCode -- cgit v1.2.3