From cdc585e0e8ceb305de83053c488ba041367b7cd6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 11 Nov 2010 02:03:58 -0800 Subject: SPARC: Clean up some historical style issues. --- src/arch/sparc/isa/base.isa | 100 ++--- src/arch/sparc/isa/decoder.isa | 557 ++++++++++++++-------------- src/arch/sparc/isa/formats/basic.isa | 9 +- src/arch/sparc/isa/formats/branch.isa | 37 +- src/arch/sparc/isa/formats/formats.isa | 22 +- src/arch/sparc/isa/formats/integerop.isa | 52 ++- src/arch/sparc/isa/formats/mem/blockmem.isa | 32 +- src/arch/sparc/isa/formats/mem/mem.isa | 8 +- src/arch/sparc/isa/formats/mem/swap.isa | 46 +-- src/arch/sparc/isa/formats/mem/util.isa | 100 +++-- src/arch/sparc/isa/formats/micro.isa | 23 +- src/arch/sparc/isa/formats/nop.isa | 2 +- src/arch/sparc/isa/formats/priv.isa | 50 ++- src/arch/sparc/isa/formats/trap.isa | 14 +- src/arch/sparc/isa/main.isa | 12 +- src/arch/sparc/isa/operands.isa | 9 +- 16 files changed, 523 insertions(+), 550 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index c6055b3a3..af70acb3d 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -119,7 +119,8 @@ output header {{ bool passesCondition(uint32_t codes, uint32_t condition); - inline int64_t sign_ext(uint64_t data, int origWidth) + inline int64_t + sign_ext(uint64_t data, int origWidth) { int shiftAmount = 64 - origWidth; return (((int64_t)data) << shiftAmount) >> shiftAmount; @@ -130,22 +131,22 @@ output decoder {{ const char *CondTestAbbrev[] = { - "nev", //Never - "e", //Equal - "le", //Less or Equal - "l", //Less - "leu", //Less or Equal Unsigned - "c", //Carry set - "n", //Negative - "o", //Overflow set - "a", //Always - "ne", //Not Equal - "g", //Greater - "ge", //Greater or Equal - "gu", //Greater Unsigned - "cc", //Carry clear - "p", //Positive - "oc" //Overflow Clear + "nev", // Never + "e", // Equal + "le", // Less or Equal + "l", // Less + "leu", // Less or Equal Unsigned + "c", // Carry set + "n", // Negative + "o", // Overflow set + "a", // Always + "ne", // Not Equal + "g", // Greater + "ge", // Greater or Equal + "gu", // Greater Unsigned + "cc", // Carry clear + "p", // Positive + "oc" // Overflow Clear }; }}; @@ -252,11 +253,10 @@ output decoder {{ void SparcStaticInst::printRegArray(std::ostream &os, const RegIndex indexArray[], int num) const { - if(num <= 0) + if (num <= 0) return; printReg(os, indexArray[0]); - for(int x = 1; x < num; x++) - { + for (int x = 1; x < num; x++) { os << ", "; printReg(os, indexArray[x]); } @@ -271,14 +271,14 @@ output decoder {{ void SparcStaticInst::printSrcReg(std::ostream &os, int reg) const { - if(_numSrcRegs > reg) + if (_numSrcRegs > reg) printReg(os, _srcRegIdx[reg]); } void SparcStaticInst::printDestReg(std::ostream &os, int reg) const { - if(_numDestRegs > reg) + if (_numDestRegs > reg) printReg(os, _destRegIdx[reg]); } @@ -291,25 +291,25 @@ output decoder {{ const int MaxInput = 32; const int MaxMicroReg = 40; if (reg < FP_Base_DepTag) { - //If we used a register from the next or previous window, - //take out the offset. + // If we used a register from the next or previous window, + // take out the offset. while (reg >= MaxMicroReg) reg -= MaxMicroReg; if (reg == FramePointerReg) ccprintf(os, "%%fp"); else if (reg == StackPointerReg) ccprintf(os, "%%sp"); - else if(reg < MaxGlobal) + else if (reg < MaxGlobal) ccprintf(os, "%%g%d", reg); - else if(reg < MaxOutput) + else if (reg < MaxOutput) ccprintf(os, "%%o%d", reg - MaxGlobal); - else if(reg < MaxLocal) + else if (reg < MaxLocal) ccprintf(os, "%%l%d", reg - MaxOutput); - else if(reg < MaxInput) + else if (reg < MaxInput) ccprintf(os, "%%i%d", reg - MaxLocal); - else if(reg < MaxMicroReg) + else if (reg < MaxMicroReg) ccprintf(os, "%%u%d", reg - MaxInput); - //The fake int regs that are really control regs + // The fake int regs that are really control regs else { switch (reg - MaxMicroReg) { case 1: @@ -435,8 +435,9 @@ output decoder {{ } } - std::string SparcStaticInst::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + SparcStaticInst::generateDisassembly(Addr pc, + const SymbolTable *symtab) const { std::stringstream ss; @@ -445,21 +446,17 @@ output decoder {{ // just print the first two source regs... if there's // a third one, it's a read-modify-write dest (Rc), // e.g. for CMOVxx - if(_numSrcRegs > 0) - { + if (_numSrcRegs > 0) printReg(ss, _srcRegIdx[0]); - } - if(_numSrcRegs > 1) - { + if (_numSrcRegs > 1) { ss << ","; printReg(ss, _srcRegIdx[1]); } // just print the first dest... if there's a second one, // it's generally implicit - if(_numDestRegs > 0) - { - if(_numSrcRegs > 0) + if (_numDestRegs > 0) { + if (_numSrcRegs > 0) ss << ","; printReg(ss, _destRegIdx[0]); } @@ -467,14 +464,14 @@ output decoder {{ return ss.str(); } - bool passesFpCondition(uint32_t fcc, uint32_t condition) + bool + passesFpCondition(uint32_t fcc, uint32_t condition) { bool u = (fcc == 3); bool g = (fcc == 2); bool l = (fcc == 1); bool e = (fcc == 0); - switch(condition) - { + switch (condition) { case FAlways: return 1; case FNever: @@ -512,7 +509,8 @@ output decoder {{ "condition code %d", condition); } - bool passesCondition(uint32_t codes, uint32_t condition) + bool + passesCondition(uint32_t codes, uint32_t condition) { CondCodes condCodes; condCodes.bits = 0; @@ -521,8 +519,7 @@ output decoder {{ condCodes.z = codes & 0x4 ? 1 : 0; condCodes.n = codes & 0x8 ? 1 : 0; - switch(condition) - { + switch (condition) { case Always: return true; case Never: @@ -567,17 +564,20 @@ output exec {{ /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled /// if not. Non-full-system mode: always returns NoFault. #if FULL_SYSTEM - inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + inline Fault + checkFpEnableFault(%(CPU_exec_context)s *xc) { Fault fault = NoFault; // dummy... this ipr access should not fault if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && - xc->readMiscReg(MISCREG_FPRS) & 0x4) + xc->readMiscReg(MISCREG_FPRS) & 0x4) { return NoFault; - else + } else { return new FpDisabled; + } } #else - inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + inline Fault + checkFpEnableFault(%(CPU_exec_context)s *xc) { return NoFault; } diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 80b29398c..e0a34a1b1 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -37,21 +37,21 @@ decode OP default Unknown::unknown() { 0x0: decode OP2 { - //Throw an illegal instruction acception + // Throw an illegal instruction acception 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); format BranchN { - //bpcc + // bpcc 0x1: decode COND2 { - //Branch Always + // Branch Always 0x8: bpa(19, annul_code={{ SparcISA::PCState pc = PCS; pc.npc(pc.pc() + disp); pc.nnpc(pc.npc() + 4); PCS = pc; }}); - //Branch Never + // Branch Never 0x0: bpn(19, {{;}}, annul_code={{ SparcISA::PCState pc = PCS; @@ -65,17 +65,17 @@ decode OP default Unknown::unknown() 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); } } - //bicc + // bicc 0x2: decode COND2 { - //Branch Always + // Branch Always 0x8: ba(22, annul_code={{ SparcISA::PCState pc = PCS; pc.npc(pc.pc() + disp); pc.nnpc(pc.npc() + 4); PCS = pc; }}); - //Branch Never + // Branch Never 0x0: bn(22, {{;}}, annul_code={{ SparcISA::PCState pc = PCS; @@ -98,19 +98,19 @@ decode OP default Unknown::unknown() 0x7: bprge(test={{Rs1.sdw >= 0}}); } } - //SETHI (or NOP if rd == 0 and imm == 0) + // SETHI (or NOP if rd == 0 and imm == 0) 0x4: SetHi::sethi({{Rd.udw = imm;}}); - //fbpfcc + // fbpfcc 0x5: decode COND2 { format BranchN { - //Branch Always + // Branch Always 0x8: fbpa(22, annul_code={{ SparcISA::PCState pc = PCS; pc.npc(pc.pc() + disp); pc.nnpc(pc.npc() + 4); PCS = pc; }}); - //Branch Never + // Branch Never 0x0: fbpn(22, {{;}}, annul_code={{ SparcISA::PCState pc = PCS; @@ -130,17 +130,17 @@ decode OP default Unknown::unknown() } } } - //fbfcc + // fbfcc 0x6: decode COND2 { format BranchN { - //Branch Always + // Branch Always 0x8: fba(22, annul_code={{ SparcISA::PCState pc = PCS; pc.npc(pc.pc() + disp); pc.nnpc(pc.npc() + 4); PCS = pc; }}); - //Branch Never + // Branch Never 0x0: fbn(22, {{;}}, annul_code={{ SparcISA::PCState pc = PCS; @@ -184,28 +184,33 @@ decode OP default Unknown::unknown() }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 0x0D: udivx({{ - if(Rs2_or_imm13 == 0) fault = new DivisionByZero; - else Rd.udw = Rs1.udw / Rs2_or_imm13; + if (Rs2_or_imm13 == 0) + fault = new DivisionByZero; + else + Rd.udw = Rs1.udw / Rs2_or_imm13; }}); 0x0E: udiv({{ - if(Rs2_or_imm13 == 0) fault = new DivisionByZero; - else - { + if (Rs2_or_imm13 == 0) { + fault = new DivisionByZero; + } else { Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; - if(Rd.udw >> 32 != 0) + if (Rd.udw >> 32 != 0) Rd.udw = 0xFFFFFFFF; } }}); 0x0F: sdiv({{ - if(Rs2_or_imm13.sdw == 0) + if (Rs2_or_imm13.sdw == 0) { fault = new DivisionByZero; - else - { - Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; - if((int64_t)Rd.udw >= std::numeric_limits::max()) + } else { + Rd.udw = ((int64_t)((Y << 32) | + Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; + if ((int64_t)Rd.udw >= + std::numeric_limits::max()) { Rd.udw = 0x7FFFFFFF; - else if((int64_t)Rd.udw <= std::numeric_limits::min()) + } else if ((int64_t)Rd.udw <= + std::numeric_limits::min()) { Rd.udw = ULL(0xFFFFFFFF80000000); + } } }}); } @@ -241,32 +246,38 @@ decode OP default Unknown::unknown() Rd = res = op1 - op2 - Ccr<0:>; }}, sub=True); 0x1D: IntOpCcRes::udivxcc({{ - if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; - else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); + if (Rs2_or_imm13.udw == 0) + fault = new DivisionByZero; + else + Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 0x1E: IntOpCcRes::udivcc({{ uint64_t resTemp; uint32_t val2 = Rs2_or_imm13.udw; int32_t overflow = 0; - if(val2 == 0) fault = new DivisionByZero; - else - { + if (val2 == 0) { + fault = new DivisionByZero; + } else { resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; overflow = (resTemp<63:32> != 0); - if(overflow) Rd = resTemp = 0xFFFFFFFF; - else Rd = resTemp; + if (overflow) + Rd = resTemp = 0xFFFFFFFF; + else + Rd = resTemp; } }}, iv={{overflow}}); 0x1F: IntOpCcRes::sdivcc({{ int64_t val2 = Rs2_or_imm13.sdw<31:0>; bool overflow = false, underflow = false; - if(val2 == 0) fault = new DivisionByZero; - else - { + if (val2 == 0) { + fault = new DivisionByZero; + } else { Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; overflow = ((int64_t)Rd >= std::numeric_limits::max()); underflow = ((int64_t)Rd <= std::numeric_limits::min()); - if(overflow) Rd = 0x7FFFFFFF; - else if(underflow) Rd = ULL(0xFFFFFFFF80000000); + if (overflow) + Rd = 0x7FFFFFFF; + else if (underflow) + Rd = ULL(0xFFFFFFFF80000000); } }}, iv={{overflow || underflow}}); 0x20: taddcc({{ @@ -288,28 +299,30 @@ decode OP default Unknown::unknown() Rd = res = op1 + op2; bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || findOverflow(32, res, op1, op2); - if(overflow) fault = new TagOverflow; + if (overflow) + fault = new TagOverflow; }}, iv={{overflow}}); 0x23: tsubcctv({{ int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; Rd = res = op1 - op2; bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || findOverflow(32, res, op1, ~op2); - if(overflow) fault = new TagOverflow; + if (overflow) + fault = new TagOverflow; }}, iv={{overflow}}, sub=True); 0x24: mulscc({{ int32_t savedLSB = Rs1<0:>; - //Step 1 + // Step 1 int64_t multiplicand = Rs2_or_imm13; - //Step 2 + // Step 2 int32_t partialP = Rs1<31:1> | ((Ccr<3:3> ^ Ccr<1:1>) << 31); - //Step 3 + // Step 3 int32_t added = Y<0:> ? multiplicand : 0; int64_t res, op1 = partialP, op2 = added; Rd = res = partialP + added; - //Steps 4 & 5 + // Steps 4 & 5 Y = Y<31:1> | (savedLSB << 31); }}); } @@ -329,59 +342,59 @@ decode OP default Unknown::unknown() } 0x28: decode RS1 { 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); - //1 should cause an illegal instruction exception + // 1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 0x05: NoPriv::rdpc({{ SparcISA::PCState pc = PCS; - if(Pstate<3:>) + if (Pstate<3:>) Rd = (pc.pc())<31:0>; else Rd = pc.pc(); }}); 0x06: NoPriv::rdfprs({{ - //Wait for all fpops to finish. + // Wait for all fpops to finish. Rd = Fprs; }}); - //7-14 should cause an illegal instruction exception + // 7-14 should cause an illegal instruction exception 0x0F: decode I { 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); } 0x10: Priv::rdpcr({{Rd = Pcr;}}); 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); - //0x12 should cause an illegal instruction exception + // 0x12 should cause an illegal instruction exception 0x13: NoPriv::rdgsr({{ fault = checkFpEnableFault(xc); if (fault) return fault; Rd = Gsr; }}); - //0x14-0x15 should cause an illegal instruction exception + // 0x14-0x15 should cause an illegal instruction exception 0x16: Priv::rdsoftint({{Rd = Softint;}}); 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 0x1A: Priv::rdstrand_sts_reg({{ - if(Pstate<2:> && !Hpstate<2:>) + if (Pstate<2:> && !Hpstate<2:>) Rd = StrandStsReg<0:>; else Rd = StrandStsReg; }}); - //0x1A is supposed to be reserved, but it reads the strand - //status register. - //0x1B-0x1F should cause an illegal instruction exception + // 0x1A is supposed to be reserved, but it reads the strand + // status register. + // 0x1B-0x1F should cause an illegal instruction exception } 0x29: decode RS1 { 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); - //0x02 should cause an illegal instruction exception + // 0x02 should cause an illegal instruction exception 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); - //0x04 should cause an illegal instruction exception + // 0x04 should cause an illegal instruction exception 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 0x06: HPriv::rdhprhver({{Rd = Hver;}}); - //0x07-0x1E should cause an illegal instruction exception + // 0x07-0x1E should cause an illegal instruction exception 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); } 0x2A: decode RS1 { @@ -400,14 +413,13 @@ decode OP default Unknown::unknown() 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); - //0x0F should cause an illegal instruction exception + // 0x0F should cause an illegal instruction exception 0x10: Priv::rdprgl({{Rd = Gl;}}); - //0x11-0x1F should cause an illegal instruction exception + // 0x11-0x1F should cause an illegal instruction exception } 0x2B: BasicOperate::flushw({{ - if(NWindows - 2 - Cansave != 0) - { - if(Otherwin) + if (NWindows - 2 - Cansave != 0) { + if (Otherwin) fault = new SpillNOther(4*Wstate<5:3>); else fault = new SpillNNormal(4*Wstate<2:0>); @@ -418,25 +430,25 @@ decode OP default Unknown::unknown() 0x0: decode CC { 0x0: movccfcc0({{ - if(passesCondition(Fsr<11:10>, COND4)) + if (passesCondition(Fsr<11:10>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; }}); 0x1: movccfcc1({{ - if(passesCondition(Fsr<33:32>, COND4)) + if (passesCondition(Fsr<33:32>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; }}); 0x2: movccfcc2({{ - if(passesCondition(Fsr<35:34>, COND4)) + if (passesCondition(Fsr<35:34>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; }}); 0x3: movccfcc3({{ - if(passesCondition(Fsr<37:36>, COND4)) + if (passesCondition(Fsr<37:36>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; @@ -445,13 +457,13 @@ decode OP default Unknown::unknown() 0x1: decode CC { 0x0: movcci({{ - if(passesCondition(Ccr<3:0>, COND4)) + if (passesCondition(Ccr<3:0>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; }}); 0x2: movccx({{ - if(passesCondition(Ccr<7:4>, COND4)) + if (passesCondition(Ccr<7:4>, COND4)) Rd = Rs2_or_imm11; else Rd = Rd; @@ -459,8 +471,10 @@ decode OP default Unknown::unknown() } } 0x2D: sdivx({{ - if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; - else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; + if (Rs2_or_imm13.sdw == 0) + fault = new DivisionByZero; + else + Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; }}); 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 0x2F: decode RCOND3 @@ -474,18 +488,18 @@ decode OP default Unknown::unknown() } 0x30: decode RD { 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); - //0x01 should cause an illegal instruction exception + // 0x01 should cause an illegal instruction exception 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); - //0x04-0x05 should cause an illegal instruction exception + // 0x04-0x05 should cause an illegal instruction exception 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); - //0x07-0x0E should cause an illegal instruction exception + // 0x07-0x0E should cause an illegal instruction exception 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); - //0x12 should cause an illegal instruction exception + // 0x12 should cause an illegal instruction exception 0x13: NoPriv::wrgsr({{ - if(Fprs<2:> == 0 || Pstate<4:> == 0) + if (Fprs<2:> == 0 || Pstate<4:> == 0) return new FpDisabled; Gsr = Rs1 ^ Rs2_or_imm13; }}); @@ -494,7 +508,7 @@ decode OP default Unknown::unknown() 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x18: NoPriv::wrstick({{ - if(!Hpstate<2:>) + if (!Hpstate<2:>) return new IllegalInstruction; Stick = Rs1 ^ Rs2_or_imm13; }}); @@ -502,16 +516,16 @@ decode OP default Unknown::unknown() 0x1A: Priv::wrstrand_sts_reg({{ StrandStsReg = Rs1 ^ Rs2_or_imm13; }}); - //0x1A is supposed to be reserved, but it writes the strand - //status register. - //0x1B-0x1F should cause an illegal instruction exception + // 0x1A is supposed to be reserved, but it writes the strand + // status register. + // 0x1B-0x1F should cause an illegal instruction exception } 0x31: decode FCN { 0x0: Priv::saved({{ assert(Cansave < NWindows - 2); assert(Otherwin || Canrestore); Cansave = Cansave + 1; - if(Otherwin == 0) + if (Otherwin == 0) Canrestore = Canrestore - 1; else Otherwin = Otherwin - 1; @@ -520,12 +534,12 @@ decode OP default Unknown::unknown() assert(Cansave || Otherwin); assert(Canrestore < NWindows - 2); Canrestore = Canrestore + 1; - if(Otherwin == 0) + if (Otherwin == 0) Cansave = Cansave - 1; else Otherwin = Otherwin - 1; - if(Cleanwin < NWindows - 1) + if (Cleanwin < NWindows - 1) Cleanwin = Cleanwin + 1; }}); } @@ -542,7 +556,7 @@ decode OP default Unknown::unknown() 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 0x07: Priv::wrprtl({{ - if(Pstate<2:> && !Hpstate<2:>) + if (Pstate<2:> && !Hpstate<2:>) Tl = std::min(Rs1 ^ Rs2_or_imm13, MaxPTL); else Tl = std::min(Rs1 ^ Rs2_or_imm13, MaxTL); @@ -554,24 +568,24 @@ decode OP default Unknown::unknown() 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); - //0x0F should cause an illegal instruction exception + // 0x0F should cause an illegal instruction exception 0x10: Priv::wrprgl({{ - if(Pstate<2:> && !Hpstate<2:>) + if (Pstate<2:> && !Hpstate<2:>) Gl = std::min(Rs1 ^ Rs2_or_imm13, MaxPGL); else Gl = std::min(Rs1 ^ Rs2_or_imm13, MaxGL); }}); - //0x11-0x1F should cause an illegal instruction exception + // 0x11-0x1F should cause an illegal instruction exception } 0x33: decode RD { 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 0x01: HPriv::wrhprhtstate( {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); - //0x02 should cause an illegal instruction exception + // 0x02 should cause an illegal instruction exception 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); - //0x04 should cause an illegal instruction exception + // 0x04 should cause an illegal instruction exception 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); - //0x06-0x01D should cause an illegal instruction exception + // 0x06-0x01D should cause an illegal instruction exception 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); } 0x34: decode OPF{ @@ -636,52 +650,52 @@ decode OP default Unknown::unknown() 0x35: decode OPF{ format FpBasic{ 0x01: fmovs_fcc0({{ - if(passesFpCondition(Fsr<11:10>, COND4)) + if (passesFpCondition(Fsr<11:10>, COND4)) Frds = Frs2s; else Frds = Frds; }}); 0x02: fmovd_fcc0({{ - if(passesFpCondition(Fsr<11:10>, COND4)) + if (passesFpCondition(Fsr<11:10>, COND4)) Frd = Frs2; else Frd = Frd; }}); 0x03: FpUnimpl::fmovq_fcc0(); 0x25: fmovrsz({{ - if(Rs1 == 0) + if (Rs1 == 0) Frds = Frs2s; else Frds = Frds; }}); 0x26: fmovrdz({{ - if(Rs1 == 0) + if (Rs1 == 0) Frd = Frs2; else Frd = Frd; }}); 0x27: FpUnimpl::fmovrqz(); 0x41: fmovs_fcc1({{ - if(passesFpCondition(Fsr<33:32>, COND4)) + if (passesFpCondition(Fsr<33:32>, COND4)) Frds = Frs2s; else Frds = Frds; }}); 0x42: fmovd_fcc1({{ - if(passesFpCondition(Fsr<33:32>, COND4)) + if (passesFpCondition(Fsr<33:32>, COND4)) Frd = Frs2; else Frd = Frd; }}); 0x43: FpUnimpl::fmovq_fcc1(); 0x45: fmovrslez({{ - if(Rs1 <= 0) + if (Rs1 <= 0) Frds = Frs2s; else Frds = Frds; }}); 0x46: fmovrdlez({{ - if(Rs1 <= 0) + if (Rs1 <= 0) Frd = Frs2; else Frd = Frd; @@ -689,161 +703,161 @@ decode OP default Unknown::unknown() 0x47: FpUnimpl::fmovrqlez(); 0x51: fcmps({{ uint8_t fcc; - if(isnan(Frs1s) || isnan(Frs2s)) + if (isnan(Frs1s) || isnan(Frs2s)) fcc = 3; - else if(Frs1s < Frs2s) + else if (Frs1s < Frs2s) fcc = 1; - else if(Frs1s > Frs2s) + else if (Frs1s > Frs2s) fcc = 2; else fcc = 0; uint8_t firstbit = 10; - if(FCMPCC) + if (FCMPCC) firstbit = FCMPCC * 2 + 30; Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); }}); 0x52: fcmpd({{ uint8_t fcc; - if(isnan(Frs1) || isnan(Frs2)) + if (isnan(Frs1) || isnan(Frs2)) fcc = 3; - else if(Frs1 < Frs2) + else if (Frs1 < Frs2) fcc = 1; - else if(Frs1 > Frs2) + else if (Frs1 > Frs2) fcc = 2; else fcc = 0; uint8_t firstbit = 10; - if(FCMPCC) + if (FCMPCC) firstbit = FCMPCC * 2 + 30; Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); }}); 0x53: FpUnimpl::fcmpq(); 0x55: fcmpes({{ uint8_t fcc = 0; - if(isnan(Frs1s) || isnan(Frs2s)) + if (isnan(Frs1s) || isnan(Frs2s)) fault = new FpExceptionIEEE754; - if(Frs1s < Frs2s) + if (Frs1s < Frs2s) fcc = 1; - else if(Frs1s > Frs2s) + else if (Frs1s > Frs2s) fcc = 2; uint8_t firstbit = 10; - if(FCMPCC) + if (FCMPCC) firstbit = FCMPCC * 2 + 30; Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); }}); 0x56: fcmped({{ uint8_t fcc = 0; - if(isnan(Frs1) || isnan(Frs2)) + if (isnan(Frs1) || isnan(Frs2)) fault = new FpExceptionIEEE754; - if(Frs1 < Frs2) + if (Frs1 < Frs2) fcc = 1; - else if(Frs1 > Frs2) + else if (Frs1 > Frs2) fcc = 2; uint8_t firstbit = 10; - if(FCMPCC) + if (FCMPCC) firstbit = FCMPCC * 2 + 30; Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); }}); 0x57: FpUnimpl::fcmpeq(); 0x65: fmovrslz({{ - if(Rs1 < 0) + if (Rs1 < 0) Frds = Frs2s; else Frds = Frds; }}); 0x66: fmovrdlz({{ - if(Rs1 < 0) + if (Rs1 < 0) Frd = Frs2; else Frd = Frd; }}); 0x67: FpUnimpl::fmovrqlz(); 0x81: fmovs_fcc2({{ - if(passesFpCondition(Fsr<35:34>, COND4)) + if (passesFpCondition(Fsr<35:34>, COND4)) Frds = Frs2s; else Frds = Frds; }}); 0x82: fmovd_fcc2({{ - if(passesFpCondition(Fsr<35:34>, COND4)) + if (passesFpCondition(Fsr<35:34>, COND4)) Frd = Frs2; else Frd = Frd; }}); 0x83: FpUnimpl::fmovq_fcc2(); 0xA5: fmovrsnz({{ - if(Rs1 != 0) + if (Rs1 != 0) Frds = Frs2s; else Frds = Frds; }}); 0xA6: fmovrdnz({{ - if(Rs1 != 0) + if (Rs1 != 0) Frd = Frs2; else Frd = Frd; }}); 0xA7: FpUnimpl::fmovrqnz(); 0xC1: fmovs_fcc3({{ - if(passesFpCondition(Fsr<37:36>, COND4)) + if (passesFpCondition(Fsr<37:36>, COND4)) Frds = Frs2s; else Frds = Frds; }}); 0xC2: fmovd_fcc3({{ - if(passesFpCondition(Fsr<37:36>, COND4)) + if (passesFpCondition(Fsr<37:36>, COND4)) Frd = Frs2; else Frd = Frd; }}); 0xC3: FpUnimpl::fmovq_fcc3(); 0xC5: fmovrsgz({{ - if(Rs1 > 0) + if (Rs1 > 0) Frds = Frs2s; else Frds = Frds; }}); 0xC6: fmovrdgz({{ - if(Rs1 > 0) + if (Rs1 > 0) Frd = Frs2; else Frd = Frd; }}); 0xC7: FpUnimpl::fmovrqgz(); 0xE5: fmovrsgez({{ - if(Rs1 >= 0) + if (Rs1 >= 0) Frds = Frs2s; else Frds = Frds; }}); 0xE6: fmovrdgez({{ - if(Rs1 >= 0) + if (Rs1 >= 0) Frd = Frs2; else Frd = Frd; }}); 0xE7: FpUnimpl::fmovrqgez(); 0x101: fmovs_icc({{ - if(passesCondition(Ccr<3:0>, COND4)) + if (passesCondition(Ccr<3:0>, COND4)) Frds = Frs2s; else Frds = Frds; }}); 0x102: fmovd_icc({{ - if(passesCondition(Ccr<3:0>, COND4)) + if (passesCondition(Ccr<3:0>, COND4)) Frd = Frs2; else Frd = Frd; }}); 0x103: FpUnimpl::fmovq_icc(); 0x181: fmovs_xcc({{ - if(passesCondition(Ccr<7:4>, COND4)) + if (passesCondition(Ccr<7:4>, COND4)) Frds = Frs2s; else Frds = Frds; }}); 0x182: fmovd_xcc({{ - if(passesCondition(Ccr<7:4>, COND4)) + if (passesCondition(Ccr<7:4>, COND4)) Frd = Frs2; else Frd = Frd; @@ -852,8 +866,8 @@ decode OP default Unknown::unknown() default: FailUnimpl::fpop2(); } } - //This used to be just impdep1, but now it's a whole bunch - //of instructions + // This used to be just impdep1, but now it's a whole bunch + // of instructions 0x36: decode OPF{ 0x00: FailUnimpl::edge8(); 0x01: FailUnimpl::edge8n(); @@ -903,27 +917,26 @@ decode OP default Unknown::unknown() 0x48: BasicOperate::faligndata({{ uint64_t msbX = Frs1.udw; uint64_t lsbX = Frs2.udw; - //Some special cases need to be split out, first - //because they're the most likely to be used, and - //second because otherwise, we end up shifting by - //greater than the width of the type being shifted, - //namely 64, which produces undefined results according - //to the C standard. - switch(Gsr<2:0>) - { - case 0: - Frd.udw = msbX; - break; - case 8: - Frd.udw = lsbX; - break; - default: - uint64_t msbShift = Gsr<2:0> * 8; - uint64_t lsbShift = (8 - Gsr<2:0>) * 8; - uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; - uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; - Frd.udw = ((msbX & msbMask) << msbShift) | - ((lsbX & lsbMask) >> lsbShift); + // Some special cases need to be split out, first + // because they're the most likely to be used, and + // second because otherwise, we end up shifting by + // greater than the width of the type being shifted, + // namely 64, which produces undefined results + // according to the C standard. + switch (Gsr<2:0>) { + case 0: + Frd.udw = msbX; + break; + case 8: + Frd.udw = lsbX; + break; + default: + uint64_t msbShift = Gsr<2:0> * 8; + uint64_t lsbShift = (8 - Gsr<2:0>) * 8; + uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; + uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; + Frd.udw = ((msbX & msbMask) << msbShift) | + ((lsbX & lsbMask) >> lsbShift); } }}); 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); @@ -1002,10 +1015,9 @@ decode OP default Unknown::unknown() } 0x38: Branch::jmpl({{ Addr target = Rs1 + Rs2_or_imm13; - if(target & 0x3) + if (target & 0x3) { fault = new MemAddressNotAligned; - else - { + } else { SparcISA::PCState pc = PCS; if (Pstate<3:>) Rd = (pc.pc())<31:0>; @@ -1017,22 +1029,17 @@ decode OP default Unknown::unknown() }}); 0x39: Branch::return({{ Addr target = Rs1 + Rs2_or_imm13; - if(fault == NoFault) - { - //Check for fills which are higher priority than alignment - //faults. - if(Canrestore == 0) - { - if(Otherwin) + if (fault == NoFault) { + // Check for fills which are higher priority than alignment + // faults. + if (Canrestore == 0) { + if (Otherwin) fault = new FillNOther(4*Wstate<5:3>); else fault = new FillNNormal(4*Wstate<2:0>); - } - //Check for alignment faults - else if(target & 0x3) + } else if (target & 0x3) { // Check for alignment faults fault = new MemAddressNotAligned; - else - { + } else { SparcISA::PCState pc = PCS; pc.nnpc(target); PCS = pc; @@ -1045,16 +1052,14 @@ decode OP default Unknown::unknown() 0x3A: decode CC { 0x0: Trap::tcci({{ - if(passesCondition(Ccr<3:0>, COND2)) - { + if (passesCondition(Ccr<3:0>, COND2)) { int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); } }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 0x2: Trap::tccx({{ - if(passesCondition(Ccr<7:4>, COND2)) - { + if (passesCondition(Ccr<7:4>, COND2)) { int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); @@ -1064,19 +1069,14 @@ decode OP default Unknown::unknown() 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, MemWriteOp); 0x3C: save({{ - if(Cansave == 0) - { - if(Otherwin) + if (Cansave == 0) { + if (Otherwin) fault = new SpillNOther(4*Wstate<5:3>); else fault = new SpillNNormal(4*Wstate<2:0>); - } - else if(Cleanwin - Canrestore == 0) - { + } else if (Cleanwin - Canrestore == 0) { fault = new CleanWindow; - } - else - { + } else { Cwp = (Cwp + 1) % NWindows; Rd_next = Rs1 + Rs2_or_imm13; Cansave = Cansave - 1; @@ -1084,15 +1084,12 @@ decode OP default Unknown::unknown() } }}); 0x3D: restore({{ - if(Canrestore == 0) - { - if(Otherwin) + if (Canrestore == 0) { + if (Otherwin) fault = new FillNOther(4*Wstate<5:3>); else fault = new FillNNormal(4*Wstate<2:0>); - } - else - { + } else { Cwp = (Cwp - 1 + NWindows) % NWindows; Rd_prev = Rs1 + Rs2_or_imm13; Cansave = Cansave + 1; @@ -1144,10 +1141,10 @@ decode OP default Unknown::unknown() 0x05: stb({{Mem.ub = Rd.sb;}}); 0x06: sth({{Mem.uhw = Rd.shw;}}); 0x07: sttw({{ - //This temporary needs to be here so that the parser - //will correctly identify this instruction as a store. - //It's probably either the parenthesis or referencing - //the member variable that throws confuses it. + // This temporary needs to be here so that the parser + // will correctly identify this instruction as a store. + // It's probably either the parenthesis or referencing + // the member variable that throws confuses it. Twin32_t temp; temp.a = RdLow<31:0>; temp.b = RdHigh<31:0>; @@ -1176,59 +1173,59 @@ decode OP default Unknown::unknown() 0x11: lduba({{Rd = Mem.ub;}}); 0x12: lduha({{Rd = Mem.uhw;}}); 0x13: decode EXT_ASI { - //ASI_LDTD_AIUP + // ASI_LDTD_AIUP 0x22: TwinLoad::ldtx_aiup( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTD_AIUS + // ASI_LDTD_AIUS 0x23: TwinLoad::ldtx_aius( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_QUAD_LDD + // ASI_QUAD_LDD 0x24: TwinLoad::ldtx_quad_ldd( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_REAL + // ASI_LDTX_REAL 0x26: TwinLoad::ldtx_real( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_N + // ASI_LDTX_N 0x27: TwinLoad::ldtx_n( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_AIUP_L + // ASI_LDTX_AIUP_L 0x2A: TwinLoad::ldtx_aiup_l( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_AIUS_L + // ASI_LDTX_AIUS_L 0x2B: TwinLoad::ldtx_aius_l( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_L + // ASI_LDTX_L 0x2C: TwinLoad::ldtx_l( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_REAL_L + // ASI_LDTX_REAL_L 0x2E: TwinLoad::ldtx_real_l( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_N_L + // ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_P + // ASI_LDTX_P 0xE2: TwinLoad::ldtx_p( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_S + // ASI_LDTX_S 0xE3: TwinLoad::ldtx_s( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_PL + // ASI_LDTX_PL 0xEA: TwinLoad::ldtx_pl( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); - //ASI_LDTX_SL + // ASI_LDTX_SL 0xEB: TwinLoad::ldtx_sl( {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}); @@ -1242,10 +1239,10 @@ decode OP default Unknown::unknown() 0x15: stba({{Mem.ub = Rd;}}); 0x16: stha({{Mem.uhw = Rd;}}); 0x17: sttwa({{ - //This temporary needs to be here so that the parser - //will correctly identify this instruction as a store. - //It's probably either the parenthesis or referencing - //the member variable that throws confuses it. + // This temporary needs to be here so that the parser + // will correctly identify this instruction as a store. + // It's probably either the parenthesis or referencing + // the member variable that throws confuses it. Twin32_t temp; temp.a = RdLow<31:0>; temp.b = RdHigh<31:0>; @@ -1304,81 +1301,81 @@ decode OP default Unknown::unknown() 0x32: ldqfa({{fault = new FpDisabled;}}); format LoadAlt { 0x33: decode EXT_ASI { - //ASI_NUCLEUS + // ASI_NUCLEUS 0x04: FailUnimpl::lddfa_n(); - //ASI_NUCLEUS_LITTLE + // ASI_NUCLEUS_LITTLE 0x0C: FailUnimpl::lddfa_nl(); - //ASI_AS_IF_USER_PRIMARY + // ASI_AS_IF_USER_PRIMARY 0x10: FailUnimpl::lddfa_aiup(); - //ASI_AS_IF_USER_PRIMARY_LITTLE + // ASI_AS_IF_USER_PRIMARY_LITTLE 0x18: FailUnimpl::lddfa_aiupl(); - //ASI_AS_IF_USER_SECONDARY + // ASI_AS_IF_USER_SECONDARY 0x11: FailUnimpl::lddfa_aius(); - //ASI_AS_IF_USER_SECONDARY_LITTLE + // ASI_AS_IF_USER_SECONDARY_LITTLE 0x19: FailUnimpl::lddfa_aiusl(); - //ASI_REAL + // ASI_REAL 0x14: FailUnimpl::lddfa_real(); - //ASI_REAL_LITTLE + // ASI_REAL_LITTLE 0x1C: FailUnimpl::lddfa_real_l(); - //ASI_REAL_IO + // ASI_REAL_IO 0x15: FailUnimpl::lddfa_real_io(); - //ASI_REAL_IO_LITTLE + // ASI_REAL_IO_LITTLE 0x1D: FailUnimpl::lddfa_real_io_l(); - //ASI_PRIMARY + // ASI_PRIMARY 0x80: FailUnimpl::lddfa_p(); - //ASI_PRIMARY_LITTLE + // ASI_PRIMARY_LITTLE 0x88: FailUnimpl::lddfa_pl(); - //ASI_SECONDARY + // ASI_SECONDARY 0x81: FailUnimpl::lddfa_s(); - //ASI_SECONDARY_LITTLE + // ASI_SECONDARY_LITTLE 0x89: FailUnimpl::lddfa_sl(); - //ASI_PRIMARY_NO_FAULT + // ASI_PRIMARY_NO_FAULT 0x82: FailUnimpl::lddfa_pnf(); - //ASI_PRIMARY_NO_FAULT_LITTLE + // ASI_PRIMARY_NO_FAULT_LITTLE 0x8A: FailUnimpl::lddfa_pnfl(); - //ASI_SECONDARY_NO_FAULT + // ASI_SECONDARY_NO_FAULT 0x83: FailUnimpl::lddfa_snf(); - //ASI_SECONDARY_NO_FAULT_LITTLE + // ASI_SECONDARY_NO_FAULT_LITTLE 0x8B: FailUnimpl::lddfa_snfl(); format BlockLoad { // LDBLOCKF - //ASI_BLOCK_AS_IF_USER_PRIMARY + // ASI_BLOCK_AS_IF_USER_PRIMARY 0x16: FailUnimpl::ldblockf_aiup(); - //ASI_BLOCK_AS_IF_USER_SECONDARY + // ASI_BLOCK_AS_IF_USER_SECONDARY 0x17: FailUnimpl::ldblockf_aius(); - //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE + // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x1E: FailUnimpl::ldblockf_aiupl(); - //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE + // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::ldblockf_aiusl(); - //ASI_BLOCK_PRIMARY + // ASI_BLOCK_PRIMARY 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); - //ASI_BLOCK_SECONDARY + // ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::ldblockf_s(); - //ASI_BLOCK_PRIMARY_LITTLE + // ASI_BLOCK_PRIMARY_LITTLE 0xF8: FailUnimpl::ldblockf_pl(); - //ASI_BLOCK_SECONDARY_LITTLE + // ASI_BLOCK_SECONDARY_LITTLE 0xF9: FailUnimpl::ldblockf_sl(); } - //LDSHORTF - //ASI_FL8_PRIMARY + // LDSHORTF + // ASI_FL8_PRIMARY 0xD0: FailUnimpl::ldshortf_8p(); - //ASI_FL8_SECONDARY + // ASI_FL8_SECONDARY 0xD1: FailUnimpl::ldshortf_8s(); - //ASI_FL8_PRIMARY_LITTLE + // ASI_FL8_PRIMARY_LITTLE 0xD8: FailUnimpl::ldshortf_8pl(); - //ASI_FL8_SECONDARY_LITTLE + // ASI_FL8_SECONDARY_LITTLE 0xD9: FailUnimpl::ldshortf_8sl(); - //ASI_FL16_PRIMARY + // ASI_FL16_PRIMARY 0xD2: FailUnimpl::ldshortf_16p(); - //ASI_FL16_SECONDARY + // ASI_FL16_SECONDARY 0xD3: FailUnimpl::ldshortf_16s(); - //ASI_FL16_PRIMARY_LITTLE + // ASI_FL16_PRIMARY_LITTLE 0xDA: FailUnimpl::ldshortf_16pl(); - //ASI_FL16_SECONDARY_LITTLE + // ASI_FL16_SECONDARY_LITTLE 0xDB: FailUnimpl::ldshortf_16sl(); - //Not an ASI which is legal with lddfa + // Not an ASI which is legal with lddfa default: Trap::lddfa_bad_asi( {{fault = new DataAccessException;}}); } @@ -1387,81 +1384,81 @@ decode OP default Unknown::unknown() 0x36: stqfa({{fault = new FpDisabled;}}); format StoreAlt { 0x37: decode EXT_ASI { - //ASI_NUCLEUS + // ASI_NUCLEUS 0x04: FailUnimpl::stdfa_n(); - //ASI_NUCLEUS_LITTLE + // ASI_NUCLEUS_LITTLE 0x0C: FailUnimpl::stdfa_nl(); - //ASI_AS_IF_USER_PRIMARY + // ASI_AS_IF_USER_PRIMARY 0x10: FailUnimpl::stdfa_aiup(); - //ASI_AS_IF_USER_PRIMARY_LITTLE + // ASI_AS_IF_USER_PRIMARY_LITTLE 0x18: FailUnimpl::stdfa_aiupl(); - //ASI_AS_IF_USER_SECONDARY + // ASI_AS_IF_USER_SECONDARY 0x11: FailUnimpl::stdfa_aius(); - //ASI_AS_IF_USER_SECONDARY_LITTLE + // ASI_AS_IF_USER_SECONDARY_LITTLE 0x19: FailUnimpl::stdfa_aiusl(); - //ASI_REAL + // ASI_REAL 0x14: FailUnimpl::stdfa_real(); - //ASI_REAL_LITTLE + // ASI_REAL_LITTLE 0x1C: FailUnimpl::stdfa_real_l(); - //ASI_REAL_IO + // ASI_REAL_IO 0x15: FailUnimpl::stdfa_real_io(); - //ASI_REAL_IO_LITTLE + // ASI_REAL_IO_LITTLE 0x1D: FailUnimpl::stdfa_real_io_l(); - //ASI_PRIMARY + // ASI_PRIMARY 0x80: FailUnimpl::stdfa_p(); - //ASI_PRIMARY_LITTLE + // ASI_PRIMARY_LITTLE 0x88: FailUnimpl::stdfa_pl(); - //ASI_SECONDARY + // ASI_SECONDARY 0x81: FailUnimpl::stdfa_s(); - //ASI_SECONDARY_LITTLE + // ASI_SECONDARY_LITTLE 0x89: FailUnimpl::stdfa_sl(); - //ASI_PRIMARY_NO_FAULT + // ASI_PRIMARY_NO_FAULT 0x82: FailUnimpl::stdfa_pnf(); - //ASI_PRIMARY_NO_FAULT_LITTLE + // ASI_PRIMARY_NO_FAULT_LITTLE 0x8A: FailUnimpl::stdfa_pnfl(); - //ASI_SECONDARY_NO_FAULT + // ASI_SECONDARY_NO_FAULT 0x83: FailUnimpl::stdfa_snf(); - //ASI_SECONDARY_NO_FAULT_LITTLE + // ASI_SECONDARY_NO_FAULT_LITTLE 0x8B: FailUnimpl::stdfa_snfl(); format BlockStore { // STBLOCKF - //ASI_BLOCK_AS_IF_USER_PRIMARY + // ASI_BLOCK_AS_IF_USER_PRIMARY 0x16: FailUnimpl::stblockf_aiup(); - //ASI_BLOCK_AS_IF_USER_SECONDARY + // ASI_BLOCK_AS_IF_USER_SECONDARY 0x17: FailUnimpl::stblockf_aius(); - //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE + // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x1E: FailUnimpl::stblockf_aiupl(); - //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE + // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::stblockf_aiusl(); - //ASI_BLOCK_PRIMARY + // ASI_BLOCK_PRIMARY 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); - //ASI_BLOCK_SECONDARY + // ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::stblockf_s(); - //ASI_BLOCK_PRIMARY_LITTLE + // ASI_BLOCK_PRIMARY_LITTLE 0xF8: FailUnimpl::stblockf_pl(); - //ASI_BLOCK_SECONDARY_LITTLE + // ASI_BLOCK_SECONDARY_LITTLE 0xF9: FailUnimpl::stblockf_sl(); } - //STSHORTF - //ASI_FL8_PRIMARY + // STSHORTF + // ASI_FL8_PRIMARY 0xD0: FailUnimpl::stshortf_8p(); - //ASI_FL8_SECONDARY + // ASI_FL8_SECONDARY 0xD1: FailUnimpl::stshortf_8s(); - //ASI_FL8_PRIMARY_LITTLE + // ASI_FL8_PRIMARY_LITTLE 0xD8: FailUnimpl::stshortf_8pl(); - //ASI_FL8_SECONDARY_LITTLE + // ASI_FL8_SECONDARY_LITTLE 0xD9: FailUnimpl::stshortf_8sl(); - //ASI_FL16_PRIMARY + // ASI_FL16_PRIMARY 0xD2: FailUnimpl::stshortf_16p(); - //ASI_FL16_SECONDARY + // ASI_FL16_SECONDARY 0xD3: FailUnimpl::stshortf_16s(); - //ASI_FL16_PRIMARY_LITTLE + // ASI_FL16_PRIMARY_LITTLE 0xDA: FailUnimpl::stshortf_16pl(); - //ASI_FL16_SECONDARY_LITTLE + // ASI_FL16_SECONDARY_LITTLE 0xDB: FailUnimpl::stshortf_16sl(); - //Not an ASI which is legal with lddfa + // Not an ASI which is legal with lddfa default: Trap::stdfa_bad_asi( {{fault = new DataAccessException;}}); } diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index cad759b3e..bef8af2cd 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -35,7 +35,8 @@ def template BasicExecDeclare {{ // Definitions of execute methods that panic. def template BasicExecPanic {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + Fault + execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); M5_DUMMY_RETURN @@ -91,7 +92,8 @@ def template BasicConstructorWithMnemonic {{ // Basic instruction class execute method template. def template BasicExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Fault + %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -101,8 +103,7 @@ def template BasicExecute {{ %(op_rd)s; %(code)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(op_wb)s; } return fault; diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa index e62e0035a..b7d0dde72 100644 --- a/src/arch/sparc/isa/formats/branch.isa +++ b/src/arch/sparc/isa/formats/branch.isa @@ -127,28 +127,29 @@ output decoder {{ template class BranchNBits<30>; - std::string Branch::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; printMnemonic(response, mnemonic); printRegArray(response, _srcRegIdx, _numSrcRegs); - if(_numDestRegs && _numSrcRegs) + if (_numDestRegs && _numSrcRegs) response << ", "; printDestReg(response, 0); return response.str(); } - std::string BranchImm13::generateDisassembly(Addr pc, + std::string + BranchImm13::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; printMnemonic(response, mnemonic); printRegArray(response, _srcRegIdx, _numSrcRegs); - if(_numSrcRegs > 0) + if (_numSrcRegs > 0) response << ", "; ccprintf(response, "0x%x", imm); if (_numDestRegs > 0) @@ -158,7 +159,8 @@ output decoder {{ return response.str(); } - std::string BranchDisp::generateDisassembly(Addr pc, + std::string + BranchDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; @@ -170,10 +172,10 @@ output decoder {{ printMnemonic(response, mnemonic); ccprintf(response, "0x%x", target); - if(symtab && symtab->findNearestSymbol(target, symbol, symbolAddr)) - { + if (symtab && + symtab->findNearestSymbol(target, symbol, symbolAddr)) { ccprintf(response, " <%s", symbol); - if(symbolAddr != target) + if (symbolAddr != target) ccprintf(response, "+%d>", target - symbolAddr); else ccprintf(response, ">"); @@ -187,7 +189,7 @@ def template JumpExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - //Attempt to execute the instruction + // Attempt to execute the instruction Fault fault = NoFault; %(op_decl)s; @@ -196,9 +198,8 @@ def template JumpExecute {{ PCS = PCS; %(code)s; - if(fault == NoFault) - { - //Write the resulting state to the execution context + if (fault == NoFault) { + // Write the resulting state to the execution context %(op_wb)s; } @@ -207,10 +208,11 @@ def template JumpExecute {{ }}; def template BranchExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Fault + %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - //Attempt to execute the instruction + // Attempt to execute the instruction Fault fault = NoFault; %(op_decl)s; @@ -222,9 +224,8 @@ def template BranchExecute {{ %(fail)s; } - if(fault == NoFault) - { - //Write the resulting state to the execution context + if (fault == NoFault) { + // Write the resulting state to the execution context %(op_wb)s; } diff --git a/src/arch/sparc/isa/formats/formats.isa b/src/arch/sparc/isa/formats/formats.isa index 8125e6349..f19e16547 100644 --- a/src/arch/sparc/isa/formats/formats.isa +++ b/src/arch/sparc/isa/formats/formats.isa @@ -26,34 +26,34 @@ // // Authors: Gabe Black -//Include the basic format -//Templates from this format are used later +// Include the basic format +// Templates from this format are used later ##include "basic.isa" -//Include base classes for microcoding instructions +// Include base classes for microcoding instructions ##include "micro.isa" -//Include the noop format +// Include the noop format ##include "nop.isa" -//Include the integerOp and integerOpCc format +// Include the integerOp and integerOpCc format ##include "integerop.isa" -//Include the memory formats +// Include the memory formats ##include "mem/mem.isa" -//Include the trap format +// Include the trap format ##include "trap.isa" -//Include the unimplemented format +// Include the unimplemented format ##include "unimp.isa" -//Include the "unknown" format +// Include the "unknown" format ##include "unknown.isa" -//Include the priveleged mode format +// Include the priveleged mode format ##include "priv.isa" -//Include the branch format +// Include the branch format ##include "branch.isa" diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 55af7e5b3..e9536f495 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -142,7 +142,7 @@ output header {{ def template SetHiDecode {{ { - if(RD == 0 && IMM22 == 0) + if (RD == 0 && IMM22 == 0) return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass)); else return (SparcStaticInst *)(new %(class_name)s(machInst)); @@ -151,11 +151,11 @@ def template SetHiDecode {{ output decoder {{ - bool IntOp::printPseudoOps(std::ostream &os, Addr pc, + bool + IntOp::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) - { + if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) { printMnemonic(os, "mov"); printSrcReg(os, 1); ccprintf(os, ", "); @@ -165,25 +165,21 @@ output decoder {{ return false; } - bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, + bool + IntOpImm::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!std::strcmp(mnemonic, "or")) - { - if(_numSrcRegs > 0 && _srcRegIdx[0] == 0) - { - if(imm == 0) + if (!std::strcmp(mnemonic, "or")) { + if (_numSrcRegs > 0 && _srcRegIdx[0] == 0) { + if (imm == 0) { printMnemonic(os, "clr"); - else - { + } else { printMnemonic(os, "mov"); ccprintf(os, " 0x%x, ", imm); } printDestReg(os, 0); return true; - } - else if(imm == 0) - { + } else if (imm == 0) { printMnemonic(os, "mov"); printSrcReg(os, 0); ccprintf(os, ", "); @@ -194,41 +190,42 @@ output decoder {{ return false; } - std::string IntOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; - if(printPseudoOps(response, pc, symtab)) + if (printPseudoOps(response, pc, symtab)) return response.str(); printMnemonic(response, mnemonic); printRegArray(response, _srcRegIdx, _numSrcRegs); - if(_numDestRegs && _numSrcRegs) + if (_numDestRegs && _numSrcRegs) response << ", "; printDestReg(response, 0); return response.str(); } - std::string IntOpImm::generateDisassembly(Addr pc, + std::string + IntOpImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; - if(printPseudoOps(response, pc, symtab)) + if (printPseudoOps(response, pc, symtab)) return response.str(); printMnemonic(response, mnemonic); printRegArray(response, _srcRegIdx, _numSrcRegs); - if(_numSrcRegs > 0) + if (_numSrcRegs > 0) response << ", "; ccprintf(response, "0x%x", imm); - if(_numDestRegs > 0) + if (_numDestRegs > 0) response << ", "; printDestReg(response, 0); return response.str(); } - std::string SetHi::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; @@ -249,9 +246,8 @@ def template IntOpExecute {{ %(op_rd)s; %(code)s; - //Write the resulting state to the execution context - if(fault == NoFault) - { + // Write the resulting state to the execution context + if (fault == NoFault) { %(cc_code)s; %(op_wb)s; } diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 020dc326f..c397d2675 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -100,8 +100,7 @@ output decoder {{ bool save = flags[IsStore]; printMnemonic(response, mnemonic); - if(save) - { + if (save) { printReg(response, _srcRegIdx[0]); ccprintf(response, ", "); } @@ -110,8 +109,7 @@ output decoder {{ ccprintf(response, " + "); printReg(response, _srcRegIdx[!save ? 1 : 2]); ccprintf(response, " ]"); - if(load) - { + if (load) { ccprintf(response, ", "); printReg(response, _destRegIdx[0]); } @@ -127,19 +125,17 @@ output decoder {{ bool save = flags[IsStore]; printMnemonic(response, mnemonic); - if(save) - { + if (save) { printReg(response, _srcRegIdx[1]); ccprintf(response, ", "); } ccprintf(response, "[ "); printReg(response, _srcRegIdx[0]); - if(imm >= 0) + if (imm >= 0) ccprintf(response, " + 0x%x ]", imm); else ccprintf(response, " + -0x%x ]", -imm); - if(load) - { + if (load) { ccprintf(response, ", "); printReg(response, _destRegIdx[0]); } @@ -156,14 +152,14 @@ def template BlockMemDeclare {{ class %(class_name)s : public %(base_class)s { public: - //Constructor + // Constructor %(class_name)s(ExtMachInst machInst); protected: class %(class_name)s_0 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_0(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s @@ -173,7 +169,7 @@ def template BlockMemDeclare {{ class %(class_name)s_1 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_1(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s @@ -183,7 +179,7 @@ def template BlockMemDeclare {{ class %(class_name)s_2 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_2(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s @@ -193,7 +189,7 @@ def template BlockMemDeclare {{ class %(class_name)s_3 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_3(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s @@ -203,7 +199,7 @@ def template BlockMemDeclare {{ class %(class_name)s_4 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_4(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s @@ -213,7 +209,7 @@ def template BlockMemDeclare {{ class %(class_name)s_5 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_5(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s @@ -223,7 +219,7 @@ def template BlockMemDeclare {{ class %(class_name)s_6 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_6(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s @@ -233,7 +229,7 @@ def template BlockMemDeclare {{ class %(class_name)s_7 : public %(base_class)sMicro { public: - //Constructor + // Constructor %(class_name)s_7(ExtMachInst machInst); %(BasicExecDeclare)s %(InitiateAccDeclare)s diff --git a/src/arch/sparc/isa/formats/mem/mem.isa b/src/arch/sparc/isa/formats/mem/mem.isa index db45e226d..17d6c5c5e 100644 --- a/src/arch/sparc/isa/formats/mem/mem.isa +++ b/src/arch/sparc/isa/formats/mem/mem.isa @@ -32,14 +32,14 @@ // Mem formats // -//Include mem utility templates and functions +// Include mem utility templates and functions ##include "util.isa" -//Include the basic memory format +// Include the basic memory format ##include "basicmem.isa" -//Include the block memory format +// Include the block memory format ##include "blockmem.isa" -//Include the load/store and cas memory format +// Include the load/store and cas memory format ##include "swap.isa" diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index 046f89822..1ab82da59 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -27,14 +27,14 @@ // Authors: Gabe Black // Ali Saidi -//This template provides the execute functions for a swap +// This template provides the execute functions for a swap def template SwapExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - //This is to support the conditional store in cas instructions. - //It should be optomized out in all the others + // This is to support the conditional store in cas instructions. + // It should be optomized out in all the others bool storeCond = true; Addr EA; %(fp_enable_check)s; @@ -45,25 +45,21 @@ def template SwapExecute {{ %(ea_code)s; DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); %(fault_check)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(code)s; } - if(storeCond && fault == NoFault) - { + if (storeCond && fault == NoFault) { %(EA_trunc)s fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, &mem_data); } - if(fault == NoFault) - { - //Handle the swapping - %(postacc_code)s; + if (fault == NoFault) { + // Handle the swapping + %(postacc_code)s; } - if(fault == NoFault) - { - //Write the resulting state to the execution context - %(op_wb)s; + if (fault == NoFault) { + // Write the resulting state to the execution context + %(op_wb)s; } return fault; @@ -86,12 +82,10 @@ def template SwapInitiateAcc {{ DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); %(fault_check)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(code)s; } - if(fault == NoFault) - { + if (fault == NoFault) { %(EA_trunc)s fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, &mem_data); @@ -111,15 +105,13 @@ def template SwapCompleteAcc {{ uint64_t mem_data = pkt->get(); - if(fault == NoFault) - { - //Handle the swapping - %(postacc_code)s; + if (fault == NoFault) { + // Handle the swapping + %(postacc_code)s; } - if(fault == NoFault) - { - //Write the resulting state to the execution context - %(op_wb)s; + if (fault == NoFault) { + // Write the resulting state to the execution context + %(op_wb)s; } return fault; diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 667b9a23a..ca673566b 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -79,21 +79,18 @@ output decoder {{ bool store = flags[IsStore]; printMnemonic(response, mnemonic); - if(store) - { + if (store) { printReg(response, _srcRegIdx[0]); ccprintf(response, ", "); } ccprintf(response, "["); - if(_srcRegIdx[!store ? 0 : 1] != 0) - { + if (_srcRegIdx[!store ? 0 : 1] != 0) { printSrcReg(response, !store ? 0 : 1); ccprintf(response, " + "); } printSrcReg(response, !store ? 1 : 2); ccprintf(response, "]"); - if(load) - { + if (load) { ccprintf(response, ", "); printReg(response, _destRegIdx[0]); } @@ -109,23 +106,20 @@ output decoder {{ bool save = flags[IsStore]; printMnemonic(response, mnemonic); - if(save) - { + if (save) { printReg(response, _srcRegIdx[0]); ccprintf(response, ", "); } ccprintf(response, "["); - if(_srcRegIdx[!save ? 0 : 1] != 0) - { + if (_srcRegIdx[!save ? 0 : 1] != 0) { printReg(response, _srcRegIdx[!save ? 0 : 1]); ccprintf(response, " + "); } - if(imm >= 0) + if (imm >= 0) ccprintf(response, "0x%x]", imm); else ccprintf(response, "-0x%x]", -imm); - if(load) - { + if (load) { ccprintf(response, ", "); printReg(response, _destRegIdx[0]); } @@ -134,7 +128,7 @@ output decoder {{ } }}; -//This template provides the execute functions for a load +// This template provides the execute functions for a load def template LoadExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const @@ -147,19 +141,16 @@ def template LoadExecute {{ %(ea_code)s; DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); %(fault_check)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(EA_trunc)s fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); } - if(fault == NoFault) - { + if (fault == NoFault) { %(code)s; } - if(fault == NoFault) - { - //Write the resulting state to the execution context - %(op_wb)s; + if (fault == NoFault) { + // Write the resulting state to the execution context + %(op_wb)s; } return fault; @@ -178,8 +169,7 @@ def template LoadInitiateAcc {{ %(ea_code)s; DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); %(fault_check)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(EA_trunc)s fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); } @@ -196,22 +186,21 @@ def template LoadCompleteAcc {{ %(op_rd)s; Mem = pkt->get(); %(code)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(op_wb)s; } return fault; } }}; -//This template provides the execute functions for a store +// This template provides the execute functions for a store def template StoreExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - //This is to support the conditional store in cas instructions. - //It should be optomized out in all the others + // This is to support the conditional store in cas instructions. + // It should be optomized out in all the others bool storeCond = true; Addr EA; %(fp_enable_check)s; @@ -220,20 +209,17 @@ def template StoreExecute {{ %(ea_code)s; DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); %(fault_check)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(code)s; } - if(storeCond && fault == NoFault) - { + if (storeCond && fault == NoFault) { %(EA_trunc)s fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, 0); } - if(fault == NoFault) - { - //Write the resulting state to the execution context - %(op_wb)s; + if (fault == NoFault) { + // Write the resulting state to the execution context + %(op_wb)s; } return fault; @@ -254,12 +240,10 @@ def template StoreInitiateAcc {{ %(ea_code)s; DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); %(fault_check)s; - if(fault == NoFault) - { + if (fault == NoFault) { %(code)s; } - if(storeCond && fault == NoFault) - { + if (storeCond && fault == NoFault) { %(EA_trunc)s fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, 0); @@ -276,17 +260,17 @@ def template StoreCompleteAcc {{ } }}; -//This delcares the initiateAcc function in memory operations +// This delcares the initiateAcc function in memory operations def template InitiateAccDeclare {{ Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; }}; -//This declares the completeAcc function in memory operations +// This declares the completeAcc function in memory operations def template CompleteAccDeclare {{ Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; }}; -//Here are some code snippets which check for various fault conditions +// Here are some code snippets which check for various fault conditions let {{ LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] StoreFuncs = [StoreExecute, StoreInitiateAcc, StoreCompleteAcc] @@ -294,15 +278,15 @@ let {{ # The LSB can be zero, since it's really the MSB in doubles and quads # and we're dealing with doubles BlockAlignmentFaultCheck = ''' - if(RD & 0xe) + if (RD & 0xe) fault = new IllegalInstruction; - else if(EA & 0x3f) + else if (EA & 0x3f) fault = new MemAddressNotAligned; ''' TwinAlignmentFaultCheck = ''' - if(RD & 0x1) + if (RD & 0x1) fault = new IllegalInstruction; - else if(EA & 0xf) + else if (EA & 0xf) fault = new MemAddressNotAligned; ''' # XXX Need to take care of pstate.hpriv as well. The lower ASIs @@ -310,10 +294,10 @@ let {{ # those that are only available in hpriv AlternateASIPrivFaultCheck = ''' if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) && - !AsiIsUnPriv((ASI)EXT_ASI)) || - (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))) + !asiIsUnPriv((ASI)EXT_ASI)) || + (!bits(Hpstate,2,2) && asiIsHPriv((ASI)EXT_ASI))) fault = new PrivilegedAction; - else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) + else if (asiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) fault = new PrivilegedAction; ''' @@ -324,18 +308,18 @@ let {{ ''' }}; -//A simple function to generate the name of the macro op of a certain -//instruction at a certain micropc +// A simple function to generate the name of the macro op of a certain +// instruction at a certain micropc let {{ def makeMicroName(name, microPc): return name + "::" + name + "_" + str(microPc) }}; -//This function properly generates the execute functions for one of the -//templates above. This is needed because in one case, ea computation, -//fault checks and the actual code all occur in the same function, -//and in the other they're distributed across two. Also note that for -//execute functions, the name of the base class doesn't matter. +// This function properly generates the execute functions for one of the +// templates above. This is needed because in one case, ea computation, +// fault checks and the actual code all occur in the same function, +// and in the other they're distributed across two. Also note that for +// execute functions, the name of the base class doesn't matter. let {{ def doSplitExecute(execute, name, Name, asi, opt_flags, microParam): microParam["asi_val"] = asi; diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index b5a53a68b..2138ba6f5 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -26,9 +26,10 @@ // // Authors: Gabe Black -//This delcares the initiateAcc function in memory operations +// This delcares the initiateAcc function in memory operations def template MacroInitiateAcc {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const + Fault + initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Tried to execute a macroop directly!\n"); return NoFault; @@ -36,17 +37,18 @@ def template MacroInitiateAcc {{ }}; def template MacroCompleteAcc {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, - Trace::InstRecord *) const + Fault + completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Tried to execute a macroop directly!\n"); return NoFault; } }}; -//This template provides the execute functions for a store +// This template provides the execute functions for a store def template MacroExecute {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + Fault + execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Tried to execute a macroop directly!\n"); return NoFault; @@ -60,7 +62,7 @@ output header {{ protected: const uint32_t numMicroops; - //Constructor. + // Constructor. SparcMacroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _numMicroops) : SparcStaticInst(mnem, _machInst, __opClass), @@ -96,7 +98,7 @@ output header {{ class SparcMicroInst : public SparcStaticInst { protected: - //Constructor. + // Constructor. SparcMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) @@ -117,7 +119,7 @@ output header {{ class SparcDelayedMicroInst : public SparcMicroInst { protected: - //Constructor. + // Constructor. SparcDelayedMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : SparcMicroInst(mnem, _machInst, __opClass) @@ -129,7 +131,8 @@ output header {{ output decoder {{ - std::string SparcMacroInst::generateDisassembly(Addr pc, + std::string + SparcMacroInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; diff --git a/src/arch/sparc/isa/formats/nop.isa b/src/arch/sparc/isa/formats/nop.isa index 63c541288..a1c650369 100644 --- a/src/arch/sparc/isa/formats/nop.isa +++ b/src/arch/sparc/isa/formats/nop.isa @@ -82,7 +82,7 @@ def template NopExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - //Nothing to see here, move along + // Nothing to see here, move along return NoFault; } }}; diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 795a22958..56f1cdbd9 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -50,12 +50,12 @@ output header {{ const SymbolTable *symtab) const; }; - //This class is for instructions that explicitly read control - //registers. It provides a special generateDisassembly function. + // This class is for instructions that explicitly read control + // registers. It provides a special generateDisassembly function. class RdPriv : public Priv { protected: - //Constructor + // Constructor RdPriv(const char *mnem, ExtMachInst _machInst, OpClass __opClass, char const * _regName) : Priv(mnem, _machInst, __opClass), regName(_regName) @@ -68,12 +68,12 @@ output header {{ char const * regName; }; - //This class is for instructions that explicitly write control - //registers. It provides a special generateDisassembly function. + // This class is for instructions that explicitly write control + // registers. It provides a special generateDisassembly function. class WrPriv : public Priv { protected: - //Constructor + // Constructor WrPriv(const char *mnem, ExtMachInst _machInst, OpClass __opClass, char const * _regName) : Priv(mnem, _machInst, __opClass), regName(_regName) @@ -102,12 +102,12 @@ output header {{ int32_t imm; }; - //This class is for instructions that explicitly write control - //registers. It provides a special generateDisassembly function. + // This class is for instructions that explicitly write control + // registers. It provides a special generateDisassembly function. class WrPrivImm : public PrivImm { protected: - //Constructor + // Constructor WrPrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, char const * _regName) : PrivImm(mnem, _machInst, __opClass), regName(_regName) @@ -122,8 +122,8 @@ output header {{ }}; output decoder {{ - std::string Priv::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; @@ -132,8 +132,8 @@ output decoder {{ return response.str(); } - std::string RdPriv::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; @@ -145,18 +145,17 @@ output decoder {{ return response.str(); } - std::string WrPriv::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; printMnemonic(response, mnemonic); ccprintf(response, " "); - //If the first reg is %g0, don't print it. - //This improves readability - if(_srcRegIdx[0] != 0) - { + // If the first reg is %g0, don't print it. + // This improves readability + if (_srcRegIdx[0] != 0) { printSrcReg(response, 0); ccprintf(response, ", "); } @@ -174,10 +173,9 @@ output decoder {{ printMnemonic(response, mnemonic); ccprintf(response, " "); - //If the first reg is %g0, don't print it. - //This improves readability - if(_srcRegIdx[0] != 0) - { + // If the first reg is %g0, don't print it. + // This improves readability + if (_srcRegIdx[0] != 0) { printSrcReg(response, 0); ccprintf(response, ", "); } @@ -203,11 +201,11 @@ def template PrivExecute {{ %(op_decl)s; %(op_rd)s; - //If the processor isn't in privileged mode, fault out right away - if(%(check)s) + // If the processor isn't in privileged mode, fault out right away + if (%(check)s) return new PrivilegedAction; - if(%(tlCheck)s) + if (%(tlCheck)s) return new IllegalInstruction; Fault fault = NoFault; diff --git a/src/arch/sparc/isa/formats/trap.isa b/src/arch/sparc/isa/formats/trap.isa index 66eff35d4..018379f57 100644 --- a/src/arch/sparc/isa/formats/trap.isa +++ b/src/arch/sparc/isa/formats/trap.isa @@ -55,8 +55,8 @@ output header {{ }}; output decoder {{ - std::string Trap::generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; @@ -71,7 +71,8 @@ output decoder {{ }}; def template TrapExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Fault + %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -83,7 +84,8 @@ def template TrapExecute {{ }}; def template FpUnimplExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Fault + %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -113,8 +115,8 @@ output header {{ { } - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const { return mnemonic; } diff --git a/src/arch/sparc/isa/main.isa b/src/arch/sparc/isa/main.isa index df5ad0c99..114dd86f8 100644 --- a/src/arch/sparc/isa/main.isa +++ b/src/arch/sparc/isa/main.isa @@ -34,7 +34,7 @@ // //////////////////////////////////////////////////////////////////// -//Include the C++ include directives +// Include the C++ include directives ##include "includes.isa" //////////////////////////////////////////////////////////////////// @@ -45,17 +45,17 @@ namespace SparcISA; -//Include the bitfield definitions +// Include the bitfield definitions ##include "bitfields.isa" -//Include the operand_types and operand definitions +// Include the operand_types and operand definitions ##include "operands.isa" -//Include the base class for sparc instructions, and some support code +// Include the base class for sparc instructions, and some support code ##include "base.isa" -//Include the definitions for the instruction formats +// Include the definitions for the instruction formats ##include "formats/formats.isa" -//Include the decoder definition +// Include the decoder definition ##include "decoder.isa" diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 8bf6450be..a72fd12b9 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -48,17 +48,20 @@ output header {{ // A function to "decompress" double and quad floating point // register numbers stuffed into 5 bit fields. These have their // MSB put in the LSB position but are otherwise normal. - static inline unsigned int dfpr(unsigned int regNum) + static inline unsigned int + dfpr(unsigned int regNum) { return (regNum & (~1)) | ((regNum & 1) << 5); } - static inline unsigned int dfprl(unsigned int regNum) + static inline unsigned int + dfprl(unsigned int regNum) { return dfpr(regNum) & (~0x1); } - static inline unsigned int dfprh(unsigned int regNum) + static inline unsigned int + dfprh(unsigned int regNum) { return dfpr(regNum) | 0x1; } -- cgit v1.2.3