From 80d9be86e616e819cc3c9a0bbc8a42a5beb41247 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 27 Sep 2008 21:03:49 -0700 Subject: gcc: Add extra parens to quell warnings. Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases. --- src/arch/sparc/isa/formats/mem/util.isa | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 38cde9a50..f2a2327ee 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -314,10 +314,11 @@ let {{ # are split into ones that are available in priv and hpriv, and # those that are only available in hpriv AlternateASIPrivFaultCheck = ''' - if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) || - !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)) - fault = new PrivilegedAction; - else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) + if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) && + !AsiIsUnPriv((ASI)EXT_ASI)) || + (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))) + fault = new PrivilegedAction; + else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) fault = new PrivilegedAction; ''' -- cgit v1.2.3 From 9c49bc7b00aa24b0488a83039ae8762d8f8094c5 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 10 Nov 2008 11:51:17 -0800 Subject: mem: update stuff for changes to Packet and Request --- src/arch/sparc/isa/formats/mem/swap.isa | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index 2ebe9aa15..046f89822 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -133,6 +133,7 @@ let {{ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] flags = string.join(mem_flags, '|') (header_output, @@ -144,6 +145,7 @@ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{ def format SwapAlt(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] mem_flags.append("EXT_ASI") flags = string.join(mem_flags, '|') (header_output, @@ -175,6 +177,7 @@ let {{ def format CasAlt(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) + mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] mem_flags.append("EXT_ASI") flags = string.join(mem_flags, '|') (header_output, -- cgit v1.2.3 From 15940d06b5f6aabbe917a2a8c4cc4bb1cab991e2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:16:04 -0800 Subject: SPARC: Adjust a few instructions to not write registers in initiateAcc. --- src/arch/sparc/isa/decoder.isa | 18 ++++++++---------- src/arch/sparc/isa/formats/mem/basicmem.isa | 10 ++++++++++ src/arch/sparc/isa/formats/mem/util.isa | 14 +++++++++----- 3 files changed, 27 insertions(+), 15 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index c35b231ff..e34ca033f 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1231,16 +1231,14 @@ decode OP default Unknown::unknown() 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 0x25: decode RD { - 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); - if (fault) - return fault; - Mem.uw = Fsr<31:0>; - Fsr = insertBits(Fsr,16,14,0);}}); - 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); - if (fault) - return fault; - Mem.udw = Fsr; - Fsr = insertBits(Fsr,16,14,0);}}); + 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc); + if (fault) + return fault; + Mem.uw = Fsr<31:0>;}}); + 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc); + if (fault) + return fault; + Mem.udw = Fsr;}}); default: FailUnimpl::stfsrOther(); } 0x26: stqf({{fault = new FpDisabled;}}); diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index e3c043cf3..c7bb3e435 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -108,6 +108,16 @@ def format Store(code, *opt_flags) {{ StoreFuncs, '', name, Name, 0, opt_flags) }}; +def format StoreFsr(code, *opt_flags) {{ + code = filterDoubles(code) + (header_output, + decoder_output, + exec_output, + decode_block) = doMemFormat(code, + StoreFuncs, '', name, Name, 0, opt_flags, + 'Fsr = insertBits(Fsr,16,14,0);') +}}; + def format TwinLoad(code, *opt_flags) {{ (header_output, decoder_output, diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index f2a2327ee..31efb9cf6 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -264,11 +264,6 @@ def template StoreInitiateAcc {{ fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, EA, %(asi_val)s, 0); } - if(fault == NoFault) - { - //Write the resulting state to the execution context - %(op_wb)s; - } return fault; } }}; @@ -277,6 +272,15 @@ def template StoreCompleteAcc {{ Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const { + Fault fault = NoFault; + %(op_decl)s; + + %(op_rd)s; + %(postacc_code)s; + if (fault == NoFault) + { + %(op_wb)s; + } return NoFault; } }}; -- cgit v1.2.3