From ecbb8debf672ee1463115319a24384eeb6b98ee3 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 6 Dec 2006 14:29:10 -0500 Subject: Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28 --- src/arch/sparc/isa/decoder.isa | 42 +++++++++------------------------ src/arch/sparc/isa/formats/mem/util.isa | 9 +++---- 2 files changed, 16 insertions(+), 35 deletions(-) (limited to 'src/arch/sparc/isa') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 781958c77..a355816ac 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -377,9 +377,7 @@ decode OP default Unknown::unknown() //1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); - 0x04: PrivCheck::rdtick( - {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}}, - {{Tick<63:>}}); + 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 0x05: NoPriv::rdpc({{ if(Pstate<3:>) Rd = (xc->readPC())<31:0>; @@ -405,15 +403,9 @@ decode OP default Unknown::unknown() }}); //0x14-0x15 should cause an illegal instruction exception 0x16: Priv::rdsoftint({{Rd = Softint;}}); - 0x17: Priv::rdtick_cmpr({{ - Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR); - }}); - 0x18: PrivCheck::rdstick({{ - Rd = xc->readMiscRegWithEffect(MISCREG_STICK); - }}, {{Stick<63:>}}); - 0x19: Priv::rdstick_cmpr({{ - Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR); - }}); + 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); + 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); + 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 0x1A: Priv::rdstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) Rd = StrandStsReg<0:>; @@ -437,9 +429,7 @@ decode OP default Unknown::unknown() 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 0x06: HPriv::rdhprhver({{Rd = Hver;}}); //0x07-0x1E should cause an illegal instruction exception - 0x1F: HPriv::rdhprhstick_cmpr({{ - Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR); - }}); + 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); } 0x2A: decode RS1 { 0x00: Priv::rdprtpc({{ @@ -462,9 +452,7 @@ decode OP default Unknown::unknown() return new IllegalInstruction; Rd = Tt; }}); - 0x04: Priv::rdprtick({{ - Rd = xc->readMiscRegWithEffect(MISCREG_TICK); - }}); + 0x04: Priv::rdprtick({{Rd = Tick;}}); 0x05: Priv::rdprtba({{Rd = Tba;}}); 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 0x07: Priv::rdprtl({{Rd = Tl;}}); @@ -554,17 +542,13 @@ decode OP default Unknown::unknown() 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); - 0x17: Priv::wrtick_cmpr({{ - xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13); - }}); + 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x18: NoPriv::wrstick({{ if(!Hpstate<2:>) return new IllegalInstruction; - xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13); - }}); - 0x19: Priv::wrstick_cmpr({{ - xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13); + Stick = Rs1 ^ Rs2_or_imm13; }}); + 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x1A: Priv::wrstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) StrandStsReg = StrandStsReg<63:1> | @@ -621,9 +605,7 @@ decode OP default Unknown::unknown() else Tt = Rs1 ^ Rs2_or_imm13; }}); - 0x04: HPriv::wrprtick({{ - xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13); - }}); + 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 0x07: Priv::wrprtl({{ @@ -660,9 +642,7 @@ decode OP default Unknown::unknown() //0x04 should cause an illegal instruction exception 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); //0x06-0x01D should cause an illegal instruction exception - 0x1F: HPriv::wrhprhstick_cmpr({{ - xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13); - }}); + 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); } 0x34: decode OPF{ format BasicOperate{ diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 3c9d33cda..3e9fd7a7d 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -148,7 +148,7 @@ def template LoadExecute {{ %(fault_check)s; if(fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); + fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); } if(fault == NoFault) { @@ -175,7 +175,7 @@ def template LoadExecute {{ %(fault_check)s; if(fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); + fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); } return fault; } @@ -288,8 +288,9 @@ let {{ # are split into ones that are available in priv and hpriv, and # those that are only available in hpriv AlternateASIPrivFaultCheck = ''' - if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0) - fault = new PrivilegedAction; + if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) || + !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)) + fault = new PrivilegedAction; else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) fault = new PrivilegedAction; ''' -- cgit v1.2.3