From ecef27f172523503eb64fc7b2d5e82c2f83b5210 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Fri, 2 Feb 2007 19:02:27 -0500
Subject: more sparc fixes

src/arch/sparc/isa/decoder.isa:
    fix rdgsr fault check
src/arch/sparc/tlb.cc:
    block asis are now supported

--HG--
extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
---
 src/arch/sparc/isa/decoder.isa | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/arch/sparc/isa')

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 57e0857f1..e56e9d81d 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -479,10 +479,10 @@ decode OP default Unknown::unknown()
                 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
                 //0x12 should cause an illegal instruction exception
                 0x13: NoPriv::rdgsr({{
-                    if(Fprs<2:> == 0 || Pstate<4:> == 0)
-                        Rd = Gsr;
-                    else
-                        fault = new FpDisabled;
+                       fault = checkFpEnableFault(xc);
+                       if (fault)
+                            return fault;
+                       Rd = Gsr;
                 }});
                 //0x14-0x15 should cause an illegal instruction exception
                 0x16: Priv::rdsoftint({{Rd = Softint;}});
-- 
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