From e04f60667af9884fa871935e4c1274bdf0311707 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 May 2006 18:40:00 -0400 Subject: Implement PR/HPR/ASR for full system Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. --HG-- extra : convert_revision : 64276a3ea884eea70112e721f85a515946ded4c2 --- src/arch/sparc/isa_traits.hh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/sparc/isa_traits.hh') diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 453d14664..2b4d89441 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -172,12 +172,12 @@ namespace SparcISA // indicate success/failure in reg the carry bit of the ccr // and put the return value itself in the standard return value reg (). if (return_value.successful()) { - // no error - regs->setMiscReg(MISCREG_CCR_XCC_C, 0); + // no error, clear XCC.C + regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) & 0xEF); regs->setIntReg(ReturnValueReg, return_value.value()); } else { - // got an error, return details - regs->setMiscReg(MISCREG_CCR_XCC_C, 1); + // got an error, set XCC.C + regs->setMiscReg(MISCREG_CCR, regs->readMiscReg(MISCREG_CCR) | 0x10); regs->setIntReg(ReturnValueReg, return_value.value()); } } -- cgit v1.2.3