From da6c1f5b096288f13bd4c608b40d1caa84c4de49 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 8 Dec 2006 14:37:31 -0500 Subject: mostly implemented SOFTINT relevant interrupt stuff. src/arch/sparc/interrupts.hh: add in thread_context.hh to get access to tc. get rid of stubs that don't make sense right now. implement checking and get softint interrupts src/arch/sparc/miscregfile.cc: softint should be OR-ed on a write. src/arch/sparc/miscregfile.hh: add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs. src/arch/sparc/ua2005.cc: implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write. --HG-- extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae --- src/arch/sparc/miscregfile.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/sparc/miscregfile.cc') diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 47b4771d9..0094f2353 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -369,7 +369,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) gsr = val; break; case MISCREG_SOFTINT: - softint = val; + softint |= val; break; case MISCREG_TICK_CMPR: tick_cmpr = val; -- cgit v1.2.3