From 03be92f23b36ba69bfee179f97cd5af23c0f6e2c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 6 Dec 2006 19:25:53 -0500 Subject: Handle access to ASI_QUEUE Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: Add function for interrupt ASIs src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: Add QUEUE asi/misc registers src/arch/sparc/regfile.cc: add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/tlb.cc: Handle access to ASI_QUEUE --HG-- extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0 --- src/arch/sparc/miscregfile.hh | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/arch/sparc/miscregfile.hh') diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 260a3344b..3b8a977cc 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -126,6 +126,17 @@ namespace SparcISA MISCREG_SCRATCHPAD_R5, MISCREG_SCRATCHPAD_R6, MISCREG_SCRATCHPAD_R7, + + /* CPU Queue Registers */ + MISCREG_QUEUE_CPU_MONDO_HEAD, + MISCREG_QUEUE_CPU_MONDO_TAIL, + MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ + MISCREG_QUEUE_DEV_MONDO_TAIL, + MISCREG_QUEUE_RES_ERROR_HEAD, + MISCREG_QUEUE_RES_ERROR_TAIL, + MISCREG_QUEUE_NRES_ERROR_HEAD, + MISCREG_QUEUE_NRES_ERROR_TAIL, + MISCREG_NUMMISCREGS }; @@ -210,6 +221,15 @@ namespace SparcISA uint64_t scratchPad[8]; + uint64_t cpu_mondo_head; + uint64_t cpu_mondo_tail; + uint64_t dev_mondo_head; + uint64_t dev_mondo_tail; + uint64_t res_error_head; + uint64_t res_error_tail; + uint64_t nres_error_head; + uint64_t nres_error_tail; + // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM -- cgit v1.2.3