From da6c1f5b096288f13bd4c608b40d1caa84c4de49 Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Fri, 8 Dec 2006 14:37:31 -0500
Subject: mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
---
src/arch/sparc/miscregfile.hh | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
(limited to 'src/arch/sparc/miscregfile.hh')
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 3b8a977cc..d09005795 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -140,6 +140,24 @@ namespace SparcISA
MISCREG_NUMMISCREGS
};
+ enum HPStateFields {
+ id = 0x800, // this impl. dependent (id) field must always be '1' for T1000
+ ibe = 0x400,
+ red = 0x20,
+ hpriv = 0x4,
+ tlz = 0x1
+ };
+
+ enum PStateFields {
+ cle = 0x200,
+ tle = 0x100,
+ mm = 0xC0,
+ pef = 0x10,
+ am = 0x8,
+ priv = 0x4,
+ ie = 0x2
+ };
+
const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
const int NumMiscRegs = MISCREG_NUMMISCREGS;
--
cgit v1.2.3