From 8e75b6e2a5137398682236e6d9a3d11b695584ea Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 4 Dec 2006 19:39:57 -0500 Subject: reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes) Protect other pieces of code so that sparc compiles SE again src/arch/sparc/SConscript: Add ua2005.cc back into SConscript src/arch/sparc/miscregfile.hh: add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness src/arch/sparc/mmaped_ipr.hh: wrap handleIpr* with if full_system so it compiles under se src/arch/sparc/ua2005.cc: reorganize edit fs only miscreg functions src/cpu/exetrace.cc: protect legion code so it doesn't try to compile under se --HG-- extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76 --- src/arch/sparc/miscregfile.hh | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/arch/sparc/miscregfile.hh') diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index e7779d333..916c23028 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -213,6 +213,10 @@ namespace SparcISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM + void setFSRegWithEffect(int miscReg, const MiscReg &val, + ThreadContext *tc); + MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc); + /** Process a tick compare event and generate an interrupt on the cpu if * appropriate. */ void processTickCompare(ThreadContext *tc); -- cgit v1.2.3