From ecbb8debf672ee1463115319a24384eeb6b98ee3 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 6 Dec 2006 14:29:10 -0500
Subject: Many more fixes for SPARC_FS. Gets us to the point where SOFTINT
 starts getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
---
 src/arch/sparc/miscregfile.hh | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'src/arch/sparc/miscregfile.hh')

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 916c23028..260a3344b 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -47,7 +47,7 @@ namespace SparcISA
     enum MiscRegIndex
     {
         /** Ancillary State Registers */
-        MISCREG_Y,
+        MISCREG_Y, /* 0 */
         MISCREG_CCR,
         MISCREG_ASI,
         MISCREG_TICK,
@@ -57,7 +57,7 @@ namespace SparcISA
         MISCREG_GSR,
         MISCREG_SOFTINT_SET,
         MISCREG_SOFTINT_CLR,
-        MISCREG_SOFTINT,
+        MISCREG_SOFTINT, /* 10 */
         MISCREG_TICK_CMPR,
         MISCREG_STICK,
         MISCREG_STICK_CMPR,
@@ -69,7 +69,7 @@ namespace SparcISA
         MISCREG_TT,
         MISCREG_PRIVTICK,
         MISCREG_TBA,
-        MISCREG_PSTATE,
+        MISCREG_PSTATE, /* 20 */
         MISCREG_TL,
         MISCREG_PIL,
         MISCREG_CWP,
@@ -81,7 +81,7 @@ namespace SparcISA
         MISCREG_GL,
 
         /** Hyper privileged registers */
-        MISCREG_HPSTATE,
+        MISCREG_HPSTATE, /* 30 */
         MISCREG_HTSTATE,
         MISCREG_HINTP,
         MISCREG_HTBA,
@@ -94,7 +94,7 @@ namespace SparcISA
 
         /** MMU Internal Registers */
         MISCREG_MMU_P_CONTEXT,
-        MISCREG_MMU_S_CONTEXT,
+        MISCREG_MMU_S_CONTEXT, /* 40 */
         MISCREG_MMU_PART_ID,
         MISCREG_MMU_LSU_CTRL,
 
@@ -105,7 +105,7 @@ namespace SparcISA
         MISCREG_MMU_ITLB_CX_TSB_PS1,
         MISCREG_MMU_ITLB_CX_CONFIG,
         MISCREG_MMU_ITLB_SFSR,
-        MISCREG_MMU_ITLB_TAG_ACCESS,
+        MISCREG_MMU_ITLB_TAG_ACCESS, /* 50 */
 
         MISCREG_MMU_DTLB_C0_TSB_PS0,
         MISCREG_MMU_DTLB_C0_TSB_PS1,
@@ -118,7 +118,7 @@ namespace SparcISA
         MISCREG_MMU_DTLB_TAG_ACCESS,
 
         /** Scratchpad regiscers **/
-        MISCREG_SCRATCHPAD_R0,
+        MISCREG_SCRATCHPAD_R0, /* 60 */
         MISCREG_SCRATCHPAD_R1,
         MISCREG_SCRATCHPAD_R2,
         MISCREG_SCRATCHPAD_R3,
-- 
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