From 8e75b6e2a5137398682236e6d9a3d11b695584ea Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 4 Dec 2006 19:39:57 -0500 Subject: reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes) Protect other pieces of code so that sparc compiles SE again src/arch/sparc/SConscript: Add ua2005.cc back into SConscript src/arch/sparc/miscregfile.hh: add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness src/arch/sparc/mmaped_ipr.hh: wrap handleIpr* with if full_system so it compiles under se src/arch/sparc/ua2005.cc: reorganize edit fs only miscreg functions src/cpu/exetrace.cc: protect legion code so it doesn't try to compile under se --HG-- extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76 --- src/arch/sparc/mmaped_ipr.hh | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/arch/sparc/mmaped_ipr.hh') diff --git a/src/arch/sparc/mmaped_ipr.hh b/src/arch/sparc/mmaped_ipr.hh index d87d127b0..b11c16754 100644 --- a/src/arch/sparc/mmaped_ipr.hh +++ b/src/arch/sparc/mmaped_ipr.hh @@ -37,6 +37,7 @@ * ISA-specific helper functions for memory mapped IPR accesses. */ +#include "config/full_system.hh" #include "cpu/thread_context.hh" #include "mem/packet.hh" #include "arch/sparc/tlb.hh" @@ -47,14 +48,22 @@ namespace SparcISA inline Tick handleIprRead(ThreadContext *xc, Packet *pkt) { +#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegRead(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif } inline Tick handleIprWrite(ThreadContext *xc, Packet *pkt) { +#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif } -- cgit v1.2.3