From 1a451cd2c5ec20c27c39a1cd3e3b5422c2b4f679 Mon Sep 17 00:00:00 2001
From: Korey Sewell <ksewell@umich.edu>
Date: Thu, 9 Jun 2011 01:34:06 -0400
Subject: sparc: compilation fixes for inorder Add a few constants and
 functions that the InOrder model wants for SPARC. * * * sparc: add eaComp
 function InOrder separates the address generation from the actual access so
 give Sparc that functionality * * * sparc: add control flags for branches
 branch predictors and other cpu model functions need to know specific
 information about branches, so add the necessary flags here

---
 src/arch/sparc/mt.hh | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 src/arch/sparc/mt.hh

(limited to 'src/arch/sparc/mt.hh')

diff --git a/src/arch/sparc/mt.hh b/src/arch/sparc/mt.hh
new file mode 100644
index 000000000..8b3d97aad
--- /dev/null
+++ b/src/arch/sparc/mt.hh
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2011 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ *
+ */
+
+#ifndef __ARCH_SPARC_MT_HH__
+#define __ARCH_SPARC_MT_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for multithreaded execution.
+ */
+
+#include <iostream>
+
+#include "arch/isa_traits.hh"
+#include "base/bitfield.hh"
+#include "base/misc.hh"
+#include "base/trace.hh"
+using namespace std;
+
+namespace SparcISA
+{
+
+template <class TC>
+inline unsigned
+getVirtProcNum(TC *tc)
+{
+    fatal("Sparc is not setup for multithreaded ISA extensions");
+    return 0;
+}
+
+
+template <class TC>
+inline unsigned
+getTargetThread(TC *tc)
+{
+    fatal("Sparc is not setup for multithreaded ISA extensions");
+    return 0;
+}
+
+} // namespace SparcISA
+
+#endif
-- 
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