From 5e8287d2e2eaf058495442ea9e32fafc343a0b53 Mon Sep 17 00:00:00 2001 From: Nathanael Premillieu Date: Wed, 5 Apr 2017 12:46:06 -0500 Subject: arch, cpu: Architectural Register structural indexing Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/2700 --- src/arch/sparc/registers.hh | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/arch/sparc/registers.hh') diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh index b25f34584..62c876f3d 100644 --- a/src/arch/sparc/registers.hh +++ b/src/arch/sparc/registers.hh @@ -59,8 +59,6 @@ typedef union MiscReg ctrlreg; } AnyReg; -typedef uint16_t RegIndex; - // semantically meaningful register indices const int ZeroReg = 0; // architecturally meaningful // the rest of these depend on the ABI @@ -78,14 +76,6 @@ const int NumCCRegs = 0; const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; -// These enumerate all the registers for dependence tracking. -enum DependenceTags { - FP_Reg_Base = NumIntRegs, - CC_Reg_Base = FP_Reg_Base + NumFloatRegs, - Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 - Max_Reg_Index = Misc_Reg_Base + NumMiscRegs, -}; - } // namespace SparcISA #endif -- cgit v1.2.3