From 4301e4cd08018eb56b4f196afcce9a8311f390b4 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Tue, 23 Jan 2007 15:50:03 -0500
Subject: use pstate.am to mask off PC/NPC where it needs to +be check
 writability of tlb cache entry before using update tagaccess in places I
 forgot to move the tlb privileged test up since it is higher priority

src/arch/sparc/faults.cc:
    save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
    return only 32 bits of PC/NPC if Pstate.am is set
    increment cleanwin correctly
src/arch/sparc/tlb.cc:
    check writability of cache entry
    update tagaccess in a few more places
    move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
    mask off upper bits of pc if pstate.am is set before comparing to legion

--HG--
extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
---
 src/arch/sparc/tlb.cc | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

(limited to 'src/arch/sparc/tlb.cc')

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 1a2ec6eac..0e59f3e15 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -549,6 +549,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 
     // were not priviledged accesing priv page
     if (!priv && e->pte.priv()) {
+        writeTagAccess(tc, vaddr, context);
         writeSfsr(tc, false, ct, false, PrivViolation, asi);
         return new InstructionAccessException;
     }
@@ -592,13 +593,15 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     // Be fast if we can!
     if (cacheValid &&  cacheState == tlbdata) {
         if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
-            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) {
+            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
+            (!write || cacheEntry[0]->pte.writable())) {
                 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
                               vaddr & cacheEntry[0]->pte.size()-1 );
                 return NoFault;
         }
         if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
-            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) {
+            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
+            (!write || cacheEntry[1]->pte.writable())) {
                 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
                               vaddr & cacheEntry[1]->pte.size()-1 );
                 return NoFault;
@@ -726,26 +729,34 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 
     }
 
+    if (!priv && e->pte.priv()) {
+        writeTagAccess(tc, vaddr, context);
+        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
+        return new DataAccessException;
+    }
 
     if (write && !e->pte.writable()) {
+        writeTagAccess(tc, vaddr, context);
         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
         return new FastDataAccessProtection;
     }
 
     if (e->pte.nofault() && !AsiIsNoFault(asi)) {
+        writeTagAccess(tc, vaddr, context);
         writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
         return new DataAccessException;
     }
 
-    if (e->pte.sideffect())
-        req->setFlags(req->getFlags() | UNCACHEABLE);
-
-
-    if (!priv && e->pte.priv()) {
-        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
+    if (e->pte.sideffect() && AsiIsNoFault(asi)) {
+        writeTagAccess(tc, vaddr, context);
+        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
         return new DataAccessException;
     }
 
+
+    if (e->pte.sideffect())
+        req->setFlags(req->getFlags() | UNCACHEABLE);
+
     // cache translation date for next translation
     cacheState = tlbdata;
     if (!cacheValid) {
-- 
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