From 7a2ecf9e268bf10fc0a2406f3a928a661e97b5fd Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 21 Feb 2007 21:06:17 -0500
Subject: add pseduo instruction support for sparc

util/m5/Makefile.alpha:
    Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
    Make the makefile more reasonable
util/m5/Makefile.alpha:
    Remove authors from copyright.
util/m5/Makefile.alpha:
    Updated Authors from bk prs info
util/m5/Makefile.alpha:
    bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
    Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
    Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
    split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
    ivle and ivlb aren't used anymore
util/m5/m5op.h:
    stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
    move the op ids into their own header file since we can share them between sparc and alpha

--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
---
 src/arch/sparc/tlb.cc | 47 +++++++++++++++++++++++++++++++----------------
 1 file changed, 31 insertions(+), 16 deletions(-)

(limited to 'src/arch/sparc/tlb.cc')

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 82b1ed175..3ed2a9cc6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -596,21 +596,36 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 
     // Be fast if we can!
     if (cacheValid &&  cacheState == tlbdata) {
-        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
-            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
-            (!write || cacheEntry[0]->pte.writable())) {
-                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
-                              vaddr & cacheEntry[0]->pte.size()-1 );
-                return NoFault;
-        }
-        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
-            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
-            (!write || cacheEntry[1]->pte.writable())) {
-                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
-                              vaddr & cacheEntry[1]->pte.size()-1 );
-                return NoFault;
-        }
-    }
+
+
+
+  if (cacheEntry[0]) {
+            TlbEntry *ce = cacheEntry[0];
+           Addr ce_va = ce->range.va;
+            if (cacheAsi[0] == asi &&
+                ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+                (!write || ce->pte.writable())) {
+                    req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+                        req->setFlags(req->getFlags() | UNCACHEABLE);
+                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+                    return NoFault;
+            } // if matched
+        } // if cache entry valid
+        if (cacheEntry[1]) {
+            TlbEntry *ce = cacheEntry[1];
+            Addr ce_va = ce->range.va;
+            if (cacheAsi[1] == asi &&
+                ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+                (!write || ce->pte.writable())) {
+                    req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+                        req->setFlags(req->getFlags() | UNCACHEABLE);
+                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+                    return NoFault;
+            } // if matched
+        } // if cache entry valid
+     }
 
     bool red = bits(tlbdata,1,1);
     bool priv = bits(tlbdata,2,2);
@@ -756,7 +771,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     }
 
 
-    if (e->pte.sideffect())
+    if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
         req->setFlags(req->getFlags() | UNCACHEABLE);
 
     // cache translation date for next translation
-- 
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