From f1aeaf7ceb44ea6ef7032048a68c74ecedc7685b Mon Sep 17 00:00:00 2001
From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Fri, 19 Jan 2007 21:33:36 -0500
Subject: some hstick and hintp changes.

src/arch/sparc/interrupts.hh:
    condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
    implement HINTP
src/arch/sparc/ua2005.cc:
    don't post interrupt unless it is enabled.

--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
---
 src/arch/sparc/ua2005.cc | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

(limited to 'src/arch/sparc/ua2005.cc')

diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index b8a891c6d..6220e6dec 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -42,10 +42,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
     switch (miscReg) {
         /* Full system only ASRs */
       case MISCREG_SOFTINT:
-        // Check if we are going to interrupt because of something
-        setReg(miscReg, val);
-        tc->getCpuPtr()->checkInterrupts = true;
-        tc->getCpuPtr()->post_interrupt(hstick_match);
+        setReg(miscReg, val);;
         if (val != 0x10000 && val != 0)
             warn("Writing to softint not really supported, writing: %#x\n", val);
         break;
@@ -53,6 +50,8 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
       case MISCREG_SOFTINT_CLR:
         return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
       case MISCREG_SOFTINT_SET:
+        tc->getCpuPtr()->checkInterrupts = true;
+        tc->getCpuPtr()->post_interrupt(soft_interrupt);
         return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
 
       case MISCREG_TICK_CMPR:
@@ -96,6 +95,9 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
       case MISCREG_HVER:
         panic("Shouldn't be writing HVER\n");
 
+      case MISCREG_HINTP:
+        setReg(miscReg, val);
+
       case MISCREG_HTBA:
         // clear lower 7 bits on writes.
         setReg(miscReg, val & ULL(~0x7FFF));
@@ -204,9 +206,11 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
     if (ticks == 0) {
         DPRINTF(Timer, "STick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
-        tc->getCpuPtr()->post_interrupt(soft_interrupt);
-        tc->getCpuPtr()->checkInterrupts = true;
-        softint |= ULL(1) << 16;
+        if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
+            tc->getCpuPtr()->post_interrupt(soft_interrupt);
+            tc->getCpuPtr()->checkInterrupts = true;
+            setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
+        }
     } else
         sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
 }
@@ -225,8 +229,11 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
     if (ticks == 0) {
         DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
-        tc->getCpuPtr()->post_interrupt(hstick_match);
-        tc->getCpuPtr()->checkInterrupts = true;
+        if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
+            setRegWithEffect(MISCREG_HINTP, 1, tc);
+            tc->getCpuPtr()->post_interrupt(hstick_match);
+            tc->getCpuPtr()->checkInterrupts = true;
+        }
         // Need to do something to cause interrupt to happen here !!! @todo
     } else
         sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
-- 
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