From ecfd628ecd394f8e7df654ffc7c342d959e12e15 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 16 Jan 2007 19:06:05 -0500 Subject: Modify ISA and staticInst to support a IsFirstMicroOp flag Increment instruction count on first micro-op instead of last src/arch/sparc/isa/decoder.isa: Implement a twin load for ASI_LDTX_P(0xe2) src/arch/sparc/isa/formats/mem/blockmem.isa: set the new flag IsFirstMicroOp when needed src/cpu/simple/atomic.cc: Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion) src/cpu/static_inst.hh: Add IsFirstMicroop flag to static insts --HG-- extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc --- src/arch/sparc/isa/decoder.isa | 3 +++ src/arch/sparc/isa/formats/mem/blockmem.isa | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 2e1344a8f..bd1a44342 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1079,6 +1079,9 @@ decode OP default Unknown::unknown() //ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + //ASI_LDTX_P + 0xE2: TwinLoad::ldtx_p( + {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); default: ldtwa({{ uint64_t val = Mem.udw; RdLow = val<31:0>; diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 5d05dad03..32421a75f 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -451,6 +451,8 @@ let {{ flag_code = '' if (microPc == 7): flag_code = "flags[IsLastMicroOp] = true;" + elif (microPc == 0): + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) @@ -492,7 +494,7 @@ let {{ flag_code = "flags[IsLastMicroOp] = true;" pcedCode = matcher.sub("RdHigh", code) else: - flag_code = "flags[IsDelayedCommit] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" pcedCode = matcher.sub("RdLow", code) iop = InstObjParams(name, Name, 'TwinMem', pcedCode, opt_flags, {"ea_code": addrCalcReg, -- cgit v1.2.3 From 0584d5bd6c24c66a0d497bba6a3a47d8cdc7a87e Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 16 Jan 2007 19:06:33 -0500 Subject: In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks --HG-- extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423 --- src/arch/sparc/tlb.cc | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 1cecb4ebb..0935cee4e 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -625,13 +625,12 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) return new DataAccessException; } - } /*else if (hpriv) {*/ - if (asi == ASI_P) { - ct = Primary; - context = pri_context; - goto continueDtbFlow; - } - //} + } + if (asi == ASI_P || asi == ASI_LDTX_P) { + ct = Primary; + context = pri_context; + goto continueDtbFlow; + } if (!implicit) { if (AsiIsLittle(asi)) @@ -640,9 +639,6 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) panic("Block ASIs not supported\n"); if (AsiIsNoFault(asi)) panic("No Fault ASIs not supported\n"); - if (write && asi == ASI_LDTX_P) - // block init store (like write hint64) - goto continueDtbFlow; if (!write && asi == ASI_QUAD_LDD) goto continueDtbFlow; -- cgit v1.2.3 From 8173a05eaf533fd9229c41c106dce0e532c49b0b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 17 Jan 2007 13:09:26 -0500 Subject: Implement reading writing of sync fault status register and address register --HG-- extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad --- src/arch/sparc/tlb.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 0935cee4e..e8b0a933b 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -876,6 +876,9 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); break; + case 0x18: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); + break; case 0x30: pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); break; @@ -889,6 +892,12 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); break; + case 0x18: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); + break; + case 0x20: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); + break; case 0x30: pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); break; @@ -1070,6 +1079,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) break; case ASI_IMMU: switch (va) { + case 0x18: + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); + break; case 0x30: tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); break; @@ -1141,6 +1153,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) break; case ASI_DMMU: switch (va) { + case 0x18: + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); + break; case 0x30: tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); break; -- cgit v1.2.3 From c8a2d602b15574bbea74ba802415a774c2e4eb38 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 17 Jan 2007 17:59:22 -0500 Subject: do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many fix for lookup table to keep it consistant with tlb on a replace of a specific entry --HG-- extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32 --- src/arch/sparc/tlb.cc | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index e8b0a933b..f64bad169 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -81,21 +81,44 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real, MapIter i; TlbEntry *new_entry = NULL; - TlbRange tr; +// TlbRange tr; int x; cacheValid = false; - tr.va = va; + /* tr.va = va; tr.size = PTE.size() - 1; tr.contextId = context_id; tr.partitionId = partition_id; tr.real = real; - +*/ DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", va, PTE.paddr(), partition_id, context_id, (int)real, entry); // Demap any entry that conflicts + for (x = 0; x < size; x++) { + if (tlb[x].range.real == real && + tlb[x].range.partitionId == partition_id && + tlb[x].range.va < va + PTE.size() - 1 && + tlb[x].range.va + tlb[x].range.size >= va && + (real || tlb[x].range.contextId == context_id )) + { + if (tlb[x].valid) { + freeList.push_front(&tlb[x]); + DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); + + tlb[x].valid = false; + if (tlb[x].used) { + tlb[x].used = false; + usedEntries--; + } + lookupTable.erase(tlb[x].range); + } + } + } + + +/* i = lookupTable.find(tr); if (i != lookupTable.end()) { i->second->valid = false; @@ -108,7 +131,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real, i->second); lookupTable.erase(i); } - +*/ if (entry != -1) { assert(entry < size && entry >= 0); @@ -127,7 +150,6 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real, } while (tlb[x].pte.locked()); lastReplaced = x; new_entry = &tlb[x]; - lookupTable.erase(new_entry->range); } /* for (x = 0; x < size; x++) { @@ -142,10 +164,15 @@ insertAllLocked: // Update the last ently if their all locked if (!new_entry) { new_entry = &tlb[size-1]; - lookupTable.erase(new_entry->range); } freeList.remove(new_entry); + if (new_entry->valid && new_entry->used) + usedEntries--; + + lookupTable.erase(new_entry->range); + + DPRINTF(TLB, "Using entry: %#X\n", new_entry); assert(PTE.valid()); @@ -315,10 +342,12 @@ TLB::invalidateAll() cacheValid = false; freeList.clear(); + lookupTable.clear(); for (x = 0; x < size; x++) { if (tlb[x].valid == true) freeList.push_back(&tlb[x]); tlb[x].valid = false; + tlb[x].used = false; } usedEntries = 0; } -- cgit v1.2.3 From ae0d8d16818e49a16a3c2fa0553acf60514934e6 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 17 Jan 2007 18:36:12 -0500 Subject: Allow ASI_LDTX_REAL --HG-- extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb --- src/arch/sparc/tlb.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index f64bad169..612345300 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -668,7 +668,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) panic("Block ASIs not supported\n"); if (AsiIsNoFault(asi)) panic("No Fault ASIs not supported\n"); - if (!write && asi == ASI_QUAD_LDD) + if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL)) goto continueDtbFlow; if (AsiIsTwin(asi)) -- cgit v1.2.3