From 8561c8366c7c9afd7e6b52b6e2385b3c1dde95a9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 25 Jan 2007 13:43:46 -0500 Subject: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back --HG-- extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4 --- src/arch/sparc/isa/decoder.isa | 64 +++++++++++++++-------------- src/arch/sparc/isa/formats/mem/blockmem.isa | 6 +-- src/arch/sparc/isa/includes.isa | 3 +- src/arch/sparc/tlb.cc | 7 +++- src/arch/sparc/tlb_map.hh | 13 ++++++ 5 files changed, 56 insertions(+), 37 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 548953982..425ebc9d0 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -186,7 +186,7 @@ decode OP default Unknown::unknown() Y = Rd<63:32>; }}); 0x0B: smul({{ - Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; + Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); Y = Rd.sdw<63:32>; }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); @@ -209,10 +209,10 @@ decode OP default Unknown::unknown() else { Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; - if(Rd.udw<63:31> != 0) + if((int64_t)Rd.udw >= std::numeric_limits::max()) Rd.udw = 0x7FFFFFFF; - else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) - Rd.udw = 0xFFFFFFFF80000000ULL; + else if((int64_t)Rd.udw <= std::numeric_limits::min()) + Rd.udw = ULL(0xFFFFFFFF80000000); } }}); } @@ -257,7 +257,7 @@ decode OP default Unknown::unknown() {{0}},{{0}},{{0}},{{0}}); 0x1B: smulcc({{ int64_t resTemp; - Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; + Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); Y = resTemp<63:32>;}}, {{0}},{{0}},{{0}},{{0}}); 0x1C: subccc({{ @@ -296,10 +296,10 @@ decode OP default Unknown::unknown() else { Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; - overflow = (Rd<63:31> != 0); - underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); + overflow = ((int64_t)Rd >= std::numeric_limits::max()); + underflow = ((int64_t)Rd <= std::numeric_limits::min()); if(overflow) Rd = 0x7FFFFFFF; - else if(underflow) Rd = 0xFFFFFFFF80000000ULL; + else if(underflow) Rd = ULL(0xFFFFFFFF80000000); } }}, {{0}}, {{overflow || underflow}}, @@ -376,7 +376,7 @@ decode OP default Unknown::unknown() 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); } 0x28: decode RS1 { - 0x00: NoPriv::rdy({{Rd = Y;}}); + 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); //1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); @@ -526,7 +526,7 @@ decode OP default Unknown::unknown() 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); } 0x30: decode RD { - 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); + 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); //0x01 should cause an illegal instruction exception 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); @@ -882,7 +882,7 @@ decode OP default Unknown::unknown() else { if (Pstate<3:>) - (Rd = xc->readPC())<31:0>; + Rd = (xc->readPC())<31:0>; else Rd = xc->readPC(); NNPC = target; @@ -1058,13 +1058,14 @@ decode OP default Unknown::unknown() 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); } 0x0D: LoadStore::ldstub( - {{Rd = Mem.ub;}}, - {{Mem.ub = 0xFF;}}); + {{uReg0 = Mem.ub;}}, + {{Rd.ub = uReg0; + Mem.ub = 0xFF;}}); 0x0E: Store::stx({{Mem.udw = Rd}}); 0x0F: LoadStore::swap( - {{uReg0 = Rd.uw; - Rd.uw = Mem.uw;}}, - {{Mem.uw = uReg0;}}); + {{ uReg0 = Mem.uw}}, + {{ Mem.uw = Rd.uw; + Rd.uw = uReg0;}}); format LoadAlt { 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); @@ -1072,34 +1073,34 @@ decode OP default Unknown::unknown() 0x13: decode EXT_ASI { //ASI_LDTD_AIUP 0x22: TwinLoad::ldtx_aiup( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTD_AIUS 0x23: TwinLoad::ldtx_aius( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_QUAD_LDD 0x24: TwinLoad::ldtx_quad_ldd( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_REAL 0x26: TwinLoad::ldtx_real( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_N 0x27: TwinLoad::ldtx_n( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_L 0x2C: TwinLoad::ldtx_l( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_REAL_L 0x2E: TwinLoad::ldtx_real_l( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_P 0xE2: TwinLoad::ldtx_p( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); //ASI_LDTX_S 0xE3: TwinLoad::ldtx_s( - {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); + {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); default: ldtwa({{ uint64_t val = Mem.udw; RdLow = val<31:0>; @@ -1120,13 +1121,14 @@ decode OP default Unknown::unknown() 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); } 0x1D: LoadStoreAlt::ldstuba( - {{Rd = Mem.ub;}}, - {{Mem.ub = 0xFF}}, {{EXT_ASI}}); + {{uReg0 = Mem.ub;}}, + {{Rd.ub = uReg0; + Mem.ub = 0xFF;}}, {{EXT_ASI}}); 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 0x1F: LoadStoreAlt::swapa( - {{uReg0 = Rd.uw; - Rd.uw = Mem.uw;}}, - {{Mem.uw = uReg0;}}, {{EXT_ASI}}); + {{ uReg0 = Mem.uw}}, + {{ Mem.uw = Rd.uw; + Rd.uw = uReg0;}}, {{EXT_ASI}}); format Trap { 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 0x21: decode X { diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 32421a75f..c36fede2e 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -476,7 +476,6 @@ let {{ faultCode = '' return (header_output, decoder_output, exec_output, decode_block) - def doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags): addrCalcReg = 'EA = Rs1 + Rs2 + offset;' addrCalcImm = 'EA = Rs1 + imm + offset;' @@ -492,10 +491,11 @@ let {{ pcedCode = '' if (microPc == 1): flag_code = "flags[IsLastMicroOp] = true;" - pcedCode = matcher.sub("RdHigh", code) + pcedCode = "RdLow = uReg0;\n" + pcedCode += matcher.sub("RdHigh", code) else: flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" - pcedCode = matcher.sub("RdLow", code) + pcedCode = matcher.sub("uReg0", code) iop = InstObjParams(name, Name, 'TwinMem', pcedCode, opt_flags, {"ea_code": addrCalcReg, "fault_check": faultCode, "micro_pc": microPc, diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 624afb693..0c112d481 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -63,6 +63,7 @@ output exec {{ #if defined(linux) #include #endif +#include #include "arch/sparc/asi.hh" #include "cpu/base.hh" diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 0e59f3e15..bf57c894f 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -170,8 +170,8 @@ insertAllLocked: freeList.remove(new_entry); if (new_entry->valid && new_entry->used) usedEntries--; - - lookupTable.erase(new_entry->range); + if (new_entry->valid) + lookupTable.erase(new_entry->range); DPRINTF(TLB, "Using entry: %#X\n", new_entry); @@ -582,6 +582,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", vaddr, size, asi); + if (lookupTable.size() != 64 - freeList.size()) + panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), + freeList.size()); if (asi == ASI_IMPLICIT) implicit = true; diff --git a/src/arch/sparc/tlb_map.hh b/src/arch/sparc/tlb_map.hh index 688daf5b9..8285db939 100644 --- a/src/arch/sparc/tlb_map.hh +++ b/src/arch/sparc/tlb_map.hh @@ -135,6 +135,19 @@ class TlbMap { return tree.empty(); } + + void print() + { + iterator i; + i = tree.begin(); + while (i != tree.end()) { + std::cout << std::hex << i->first.va << " " << i->first.size << " " << + i->first.contextId << " " << i->first.partitionId << " " << + i->first.real << " " << i->second << std::endl; + i++; + } + } + }; }; -- cgit v1.2.3 From 202d7f62b9ea11e6b72c4b15ff818549ea14f038 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 26 Jan 2007 12:51:07 -0500 Subject: eliminate cpu checkInterrupts bool, it is redundant and unnecessary. --HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719 --- src/arch/sparc/ua2005.cc | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 6220e6dec..b583da8b0 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -50,7 +50,6 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_SOFTINT_CLR: return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); case MISCREG_SOFTINT_SET: - tc->getCpuPtr()->checkInterrupts = true; tc->getCpuPtr()->post_interrupt(soft_interrupt); return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); @@ -80,15 +79,9 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_PSTATE: - if (val & PSTATE::ie && !(pstate & PSTATE::ie)) { - tc->getCpuPtr()->checkInterrupts = true; - } setReg(miscReg, val); case MISCREG_PIL: - if (val < pil) { - tc->getCpuPtr()->checkInterrupts = true; - } setReg(miscReg, val); break; @@ -112,7 +105,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: setReg(miscReg, val); - tc->getCpuPtr()->checkInterrupts = true; + //do something to post mondo interrupt break; case MISCREG_HSTICK_CMPR: @@ -208,7 +201,6 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) (stick_cmpr & mask(63))); if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { tc->getCpuPtr()->post_interrupt(soft_interrupt); - tc->getCpuPtr()->checkInterrupts = true; setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } } else @@ -232,7 +224,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { setRegWithEffect(MISCREG_HINTP, 1, tc); tc->getCpuPtr()->post_interrupt(hstick_match); - tc->getCpuPtr()->checkInterrupts = true; } // Need to do something to cause interrupt to happen here !!! @todo } else -- cgit v1.2.3 From 63fdabf191b8ac1031fb25da61ab2526d4bb6d05 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 18:48:51 -0500 Subject: make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd --- src/arch/sparc/isa/decoder.isa | 4 ++-- src/arch/sparc/isa/formats/basic.isa | 3 ++- src/arch/sparc/isa/formats/integerop.isa | 6 +++--- src/arch/sparc/isa/includes.isa | 4 +++- src/arch/sparc/isa_traits.hh | 2 +- src/arch/sparc/system.cc | 1 + src/arch/sparc/tlb.cc | 4 +++- src/arch/sparc/utility.hh | 2 +- 8 files changed, 16 insertions(+), 10 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index bd1a44342..bfb8252b9 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -685,8 +685,8 @@ decode OP default Unknown::unknown() Fsr &= ~(0x1F); }}); 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); - 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}}); - 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); + 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); + 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index a4c05387b..9805c7c0b 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -38,6 +38,7 @@ def template BasicExecPanic {{ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Execute method called when it shouldn't!"); + M5_DUMMY_RETURN } }}; diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 4f8ebebcc..9470fc55f 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -154,7 +154,7 @@ output decoder {{ bool IntOp::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) + if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) { printMnemonic(os, "mov"); printSrcReg(os, 1); @@ -168,7 +168,7 @@ output decoder {{ bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc, const SymbolTable *symbab) const { - if(!strcmp(mnemonic, "or")) + if(!std::strcmp(mnemonic, "or")) { if(_numSrcRegs > 0 && _srcRegIdx[0] == 0) { diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 624afb693..688f26d5c 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -34,6 +34,7 @@ // output header {{ +#include #include #include @@ -64,6 +65,7 @@ output exec {{ #include #endif +#include #include "arch/sparc/asi.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 3f0b9cad5..ea15fac10 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -59,7 +59,7 @@ namespace SparcISA // These enumerate all the registers for dependence tracking. enum DependenceTags { FP_Base_DepTag = 33, - Ctrl_Base_DepTag = 97, + Ctrl_Base_DepTag = 97 }; // semantically meaningful register indices diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index da83d86fc..800d47c15 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -195,6 +195,7 @@ bool SparcSystem::breakpoint() { panic("Need to implement"); + M5_DUMMY_RETURN } void diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 612345300..dc4c9ef1f 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -28,6 +28,8 @@ * Authors: Ali Saidi */ +#include + #include "arch/sparc/asi.hh" #include "arch/sparc/miscregfile.hh" #include "arch/sparc/tlb.hh" @@ -53,7 +55,7 @@ TLB::TLB(const std::string &name, int s) fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); tlb = new TlbEntry[size]; - memset(tlb, 0, sizeof(TlbEntry) * size); + std::memset(tlb, 0, sizeof(TlbEntry) * size); for (int x = 0; x < size; x++) freeList.push_back(&tlb[x]); diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 5c7fe343d..3c8bdcd01 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -50,7 +50,7 @@ namespace SparcISA inline ExtMachInst makeExtMI(MachInst inst, ThreadContext * xc) { - ExtMachInst emi = (unsigned MachInst) inst; + ExtMachInst emi = (MachInst) inst; //The I bit, bit 13, is used to figure out where the ASI //should come from. Use that in the ExtMachInst. This is //slightly redundant, but it removes the need to put a condition -- cgit v1.2.3 From 2939d7d061efc8444c06ac52f82c8aeaf0048aaf Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 18:57:16 -0500 Subject: Make Sparc traceflag even more chatty some fixes to fp instructions to use the single precision registers if this is an fp op emit fp check code add fpregs to m5legion struct src/arch/sparc/floatregfile.cc: Make Sparc traceflag even more chatty src/arch/sparc/isa/base.isa: add code to check if the fpu is enabled src/arch/sparc/isa/decoder.isa: some fixes to fp instructions to use the single precision registers fix smul again fix subc/subcc/subccc condition code setting src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/mem/util.isa: if this is an fp op emit fp check code src/cpu/exetrace.cc: check fp regs as well as int regs src/cpu/m5legion_interface.h: add fpregs to m5legion struct --HG-- extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232 --- src/arch/sparc/floatregfile.cc | 6 ++++++ src/arch/sparc/isa/base.isa | 26 +++++++++++++++++++++++++- src/arch/sparc/isa/decoder.isa | 25 ++++++++++++------------- src/arch/sparc/isa/formats/basic.isa | 3 ++- src/arch/sparc/isa/formats/mem/util.isa | 6 +++++- 5 files changed, 50 insertions(+), 16 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc index 7f3d5a758..1bb78c67b 100644 --- a/src/arch/sparc/floatregfile.cc +++ b/src/arch/sparc/floatregfile.cc @@ -72,16 +72,19 @@ FloatReg FloatRegFile::readReg(int floatReg, int width) float32_t result32; memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); result = htog(result32); + DPRINTF(Sparc, "Read FP32 register %d = 0x%x\n", floatReg, result); break; case DoubleWidth: float64_t result64; memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); result = htog(result64); + DPRINTF(Sparc, "Read FP64 register %d = 0x%x\n", floatReg, result); break; case QuadWidth: float128_t result128; memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); result = htog(result128); + DPRINTF(Sparc, "Read FP128 register %d = 0x%x\n", floatReg, result); break; default: panic("Attempted to read a %d bit floating point register!", width); @@ -101,16 +104,19 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) uint32_t result32; memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); result = htog(result32); + DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result); break; case DoubleWidth: uint64_t result64; memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); result = htog(result64); + DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result); break; case QuadWidth: uint64_t result128; memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); result = htog(result128); + DPRINTF(Sparc, "Read FP128 bits register %d = 0x%x\n", floatReg, result); break; default: panic("Attempted to read a %d bit floating point register!", width); diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index 4a806bfd0..5b65ec288 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -290,3 +290,27 @@ output decoder {{ } }}; +output exec {{ + /// Check "FP enabled" machine status bit. Called when executing any FP + /// instruction in full-system mode. + /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled + /// if not. Non-full-system mode: always returns NoFault. +#if FULL_SYSTEM + inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + { + Fault fault = NoFault; // dummy... this ipr access should not fault + if (xc->readMiscRegWithEffect(MISCREG_PSTATE) & PSTATE::pef && + xc->readMiscRegWithEffect(MISCREG_FPRS) & 0x4) + return NoFault; + else + return new FpDisabled; + } +#else + inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + { + return NoFault; + } +#endif +}}; + + diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 425ebc9d0..852fddfcf 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -186,7 +186,7 @@ decode OP default Unknown::unknown() Y = Rd<63:32>; }}); 0x0B: smul({{ - Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); + Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); Y = Rd.sdw<63:32>; }}); 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); @@ -246,8 +246,7 @@ decode OP default Unknown::unknown() Rd = resTemp = Rs1 + val2 + carryin;}}, {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, - {{(Rs1<63:1> + val2<63:1> + - ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, + {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} ); 0x1A: umulcc({{ @@ -257,16 +256,16 @@ decode OP default Unknown::unknown() {{0}},{{0}},{{0}},{{0}}); 0x1B: smulcc({{ int64_t resTemp; - Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13); + Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); Y = resTemp<63:32>;}}, {{0}},{{0}},{{0}},{{0}}); 0x1C: subccc({{ int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = Ccr<0:0>; Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, - {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, + {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, + {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} ); 0x1D: udivxcc({{ @@ -664,7 +663,7 @@ decode OP default Unknown::unknown() Fsr &= ~(7 << 14); Fsr &= ~(0x1F); }}); - 0x03: Trap::fmovq({{fault = new FpDisabled;}}); + 0x03: Trap::fmovq({{fault = new FpExceptionOther;}}); 0x05: fnegs({{ Frds.uw = Frs2s.uw ^ (1UL << 31); //fsr.ftt = fsr.cexc = 0 @@ -860,11 +859,11 @@ decode OP default Unknown::unknown() 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); - 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}}); + 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}}); 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); - 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}}); + 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}}); 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 0x7C: Trap::for({{fault = new IllegalInstruction;}}); @@ -1130,14 +1129,14 @@ decode OP default Unknown::unknown() {{ Mem.uw = Rd.uw; Rd.uw = uReg0;}}, {{EXT_ASI}}); format Trap { - 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); + 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 0x21: decode X { 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); } 0x22: ldqf({{fault = new FpDisabled;}}); 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); - 0x24: Store::stf({{Mem.uw = Frd.uw;}}); + 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 0x25: decode X { 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); @@ -1145,7 +1144,7 @@ decode OP default Unknown::unknown() 0x26: stqf({{fault = new FpDisabled;}}); 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 0x2D: Nop::prefetch({{ }}); - 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}}); + 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 0x32: ldqfa({{fault = new FpDisabled;}}); format LoadAlt { 0x33: decode EXT_ASI { @@ -1228,7 +1227,7 @@ decode OP default Unknown::unknown() {{fault = new DataAccessException;}}); } } - 0x34: Store::stfa({{Mem.uw = Frd.uw;}}); + 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 0x36: stqfa({{fault = new FpDisabled;}}); format StoreAlt { 0x37: decode EXT_ASI { diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index a4c05387b..db6efd229 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -71,6 +71,7 @@ def template BasicExecute {{ { Fault fault = NoFault; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(code)s; diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index b6e0945b7..3b02f58de 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -141,6 +141,7 @@ def template LoadExecute {{ { Fault fault = NoFault; Addr EA; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -169,6 +170,7 @@ def template LoadExecute {{ Fault fault = NoFault; Addr EA; uint%(mem_acc_size)s_t Mem; + %(fp_enable_check)s; %(ea_decl)s; %(ea_rd)s; %(ea_code)s; @@ -206,6 +208,7 @@ def template StoreExecute {{ //It should be optomized out in all the others bool storeCond = true; Addr EA; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(ea_code)s; @@ -235,6 +238,7 @@ def template StoreExecute {{ Fault fault = NoFault; bool storeCond = true; Addr EA; + %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(ea_code)s; -- cgit v1.2.3