From 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU. --- src/arch/sparc/SConscript | 1 + src/arch/sparc/isa.cc | 147 ++++++++++++++++++++++++++++++++++++++++++++++ src/arch/sparc/isa.hh | 87 +++++++++++++++++++++++++++ src/arch/sparc/regfile.cc | 92 ----------------------------- src/arch/sparc/regfile.hh | 28 --------- 5 files changed, 235 insertions(+), 120 deletions(-) create mode 100644 src/arch/sparc/isa.cc create mode 100644 src/arch/sparc/isa.hh (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 940cf2076..eb0d21598 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -36,6 +36,7 @@ if env['TARGET_ISA'] == 'sparc': Source('faults.cc') Source('floatregfile.cc') Source('intregfile.cc') + Source('isa.cc') Source('miscregfile.cc') Source('pagetable.cc') Source('regfile.cc') diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc new file mode 100644 index 000000000..3aeeb14ab --- /dev/null +++ b/src/arch/sparc/isa.cc @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/sparc/isa.hh" +#include "cpu/thread_context.hh" + +namespace SparcISA +{ + +void +ISA::clear() +{ + miscRegFile.clear(); +} + +MiscReg +ISA::readMiscRegNoEffect(int miscReg) +{ + return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg); +} + +MiscReg +ISA::readMiscReg(int miscReg, ThreadContext *tc) +{ + return miscRegFile.readReg((MiscRegIndex)miscReg, tc); +} + +void +ISA::setMiscRegNoEffect(int miscReg, const MiscReg val) +{ + miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val); +} + +void +ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc) +{ + miscRegFile.setReg((MiscRegIndex)miscReg, val, tc); +} + +int +ISA::flattenIntIndex(int reg) +{ + int gl = miscRegFile.readRegNoEffect(MISCREG_GL); + int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP); + //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); + int newReg; + //The total number of global registers + int numGlobals = (MaxGL + 1) * 8; + if(reg < 8) + { + //Global register + //Put it in the appropriate set of globals + newReg = reg + gl * 8; + } + else if(reg < NumIntArchRegs) + { + //Regular windowed register + //Put it in the window pointed to by cwp + newReg = numGlobals + + ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16)); + } + else if(reg < NumIntArchRegs + NumMicroIntRegs) + { + //Microcode register + //Displace from the end of the regular registers + newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16; + } + else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs) + { + reg -= (NumIntArchRegs + NumMicroIntRegs); + if(reg < 8) + { + //Global register from the next window + //Put it in the appropriate set of globals + newReg = reg + gl * 8; + } + else + { + //Windowed register from the previous window + //Put it in the window before the one pointed to by cwp + newReg = numGlobals + + ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16)); + } + } + else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs) + { + reg -= (2 * NumIntArchRegs + NumMicroIntRegs); + if(reg < 8) + { + //Global register from the previous window + //Put it in the appropriate set of globals + newReg = reg + gl * 8; + } + else + { + //Windowed register from the next window + //Put it in the window after the one pointed to by cwp + newReg = numGlobals + + ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16)); + } + } + else + panic("Tried to flatten invalid register index %d!\n", reg); + DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg); + return newReg; +} + +void +ISA::serialize(EventManager *em, std::ostream &os) +{ + miscRegFile.serialize(em, os); +} + +void +ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) +{ + miscRegFile.unserialize(em, cp, section); +} + +} diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh new file mode 100644 index 000000000..1dbfe7a28 --- /dev/null +++ b/src/arch/sparc/isa.hh @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_SPARC_ISA_HH__ +#define __ARCH_SPARC_ISA_HH__ + +#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/types.hh" + +class Checkpoint; +class EventManager; + +namespace SparcISA +{ + class ISA + { + protected: + MiscRegFile miscRegFile; + + public: + + int instAsid() + { + return miscRegFile.getInstAsid(); + } + + int dataAsid() + { + return miscRegFile.getDataAsid(); + } + + void clear(); + + MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); + + void setMiscRegNoEffect(int miscReg, const MiscReg val); + void setMiscReg(int miscReg, const MiscReg val, + ThreadContext *tc); + + int flattenIntIndex(int reg); + + int + flattenFloatIndex(int reg) + { + return reg; + } + + void serialize(EventManager *em, std::ostream &os); + void unserialize(EventManager *em, Checkpoint *cp, + const std::string §ion); + + ISA() + { + clear(); + } + }; +} + +#endif diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index a88c6c931..1daa43818 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -72,28 +72,6 @@ void RegFile::clear() { floatRegFile.clear(); intRegFile.clear(); - miscRegFile.clear(); -} - -MiscReg RegFile::readMiscRegNoEffect(int miscReg) -{ - return miscRegFile.readRegNoEffect(miscReg); -} - -MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc) -{ - return miscRegFile.readReg(miscReg, tc); -} - -void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val) -{ - miscRegFile.setRegNoEffect(miscReg, val); -} - -void RegFile::setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc) -{ - miscRegFile.setReg(miscReg, val, tc); } FloatReg RegFile::readFloatReg(int floatReg, int width) @@ -151,80 +129,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val) intRegFile.setReg(intReg, val); } -int SparcISA::flattenIntIndex(ThreadContext * tc, int reg) -{ - int gl = tc->readMiscRegNoEffect(MISCREG_GL); - int cwp = tc->readMiscRegNoEffect(MISCREG_CWP); - //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); - int newReg; - //The total number of global registers - int numGlobals = (MaxGL + 1) * 8; - if(reg < 8) - { - //Global register - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else if(reg < NumIntArchRegs) - { - //Regular windowed register - //Put it in the window pointed to by cwp - newReg = numGlobals + - ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16)); - } - else if(reg < NumIntArchRegs + NumMicroIntRegs) - { - //Microcode register - //Displace from the end of the regular registers - newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16; - } - else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the next window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the previous window - //Put it in the window before the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (2 * NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the previous window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the next window - //Put it in the window after the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else - panic("Tried to flatten invalid register index %d!\n", reg); - DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg); - return newReg; - //return intRegFile.flattenIndex(reg); -} - void RegFile::serialize(EventManager *em, ostream &os) { intRegFile.serialize(os); floatRegFile.serialize(os); - miscRegFile.serialize(em, os); SERIALIZE_SCALAR(pc); SERIALIZE_SCALAR(npc); SERIALIZE_SCALAR(nnpc); @@ -235,7 +144,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) { intRegFile.unserialize(cp, section); floatRegFile.unserialize(cp, section); - miscRegFile.unserialize(em, cp, section); UNSERIALIZE_SCALAR(pc); UNSERIALIZE_SCALAR(npc); UNSERIALIZE_SCALAR(nnpc); diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 7da302eb7..2333d9da5 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -65,31 +65,11 @@ namespace SparcISA protected: IntRegFile intRegFile; // integer register file FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file public: void clear(); - MiscReg readMiscRegNoEffect(int miscReg); - - MiscReg readMiscReg(int miscReg, ThreadContext *tc); - - void setMiscRegNoEffect(int miscReg, const MiscReg &val); - - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc); - - int instAsid() - { - return miscRegFile.getInstAsid(); - } - - int dataAsid() - { - return miscRegFile.getDataAsid(); - } - FloatReg readFloatReg(int floatReg, int width); FloatReg readFloatReg(int floatReg); @@ -117,14 +97,6 @@ namespace SparcISA public: }; - int flattenIntIndex(ThreadContext * tc, int reg); - - static inline int - flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); -- cgit v1.2.3 From 25884a87733cd35ef6613aaef9a8a08194267552 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Get rid of the float register width parameter. --- src/arch/sparc/floatregfile.cc | 139 ++++------------------------------------- src/arch/sparc/floatregfile.hh | 28 +++------ src/arch/sparc/regfile.cc | 33 ++-------- src/arch/sparc/regfile.hh | 8 --- src/arch/sparc/types.hh | 4 +- 5 files changed, 25 insertions(+), 187 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc index 2d1af2218..6fdc36489 100644 --- a/src/arch/sparc/floatregfile.cc +++ b/src/arch/sparc/floatregfile.cc @@ -43,155 +43,38 @@ class Checkpoint; void FloatRegFile::clear() { - memset(regSpace, 0, sizeof(regSpace)); + memset(regs.q, 0, sizeof(regs.q)); } -FloatReg FloatRegFile::readReg(int floatReg, int width) +FloatReg FloatRegFile::readReg(int floatReg) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatReg result; - switch(width) - { - case SingleWidth: - uint32_t result32; - float32_t fresult32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result32 = htog(result32); - memcpy(&fresult32, &result32, sizeof(result32)); - result = fresult32; - DPRINTF(FloatRegs, "Read FP32 register %d = [%f]0x%x\n", - floatReg, result, result32); - break; - case DoubleWidth: - uint64_t result64; - float64_t fresult64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result64 = htog(result64); - memcpy(&fresult64, &result64, sizeof(result64)); - result = fresult64; - DPRINTF(FloatRegs, "Read FP64 register %d = [%f]0x%x\n", - floatReg, result, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; + return regs.s[floatReg]; } -FloatRegBits FloatRegFile::readRegBits(int floatReg, int width) +FloatRegBits FloatRegFile::readRegBits(int floatReg) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - FloatRegBits result; - switch(width) - { - case SingleWidth: - uint32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); - result = htog(result32); - DPRINTF(FloatRegs, "Read FP32 bits register %d = 0x%x\n", - floatReg, result); - break; - case DoubleWidth: - uint64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); - result = htog(result64); - DPRINTF(FloatRegs, "Read FP64 bits register %d = 0x%x\n", - floatReg, result); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } - return result; + return regs.q[floatReg]; } -Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width) +Fault FloatRegFile::setReg(int floatReg, const FloatReg &val) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - - uint32_t result32; - uint64_t result64; - float32_t fresult32; - float64_t fresult64; - switch(width) - { - case SingleWidth: - fresult32 = val; - memcpy(&result32, &fresult32, sizeof(result32)); - result32 = gtoh(result32); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - fresult64 = val; - memcpy(&result64, &fresult64, sizeof(result64)); - result64 = gtoh(result64); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } + regs.s[floatReg] = val; return NoFault; } -Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width) +Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val) { - //In each of these cases, we have to copy the value into a temporary - //variable. This is because we may otherwise try to access an - //unaligned portion of memory. - uint32_t result32; - uint64_t result64; - switch(width) - { - case SingleWidth: - result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result32); - break; - case DoubleWidth: - result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); - DPRINTF(FloatRegs, "Write FP64 bits register %d = 0x%x\n", - floatReg, result64); - break; - case QuadWidth: - panic("Quad width FP not implemented."); - break; - default: - panic("Attempted to read a %d bit floating point register!", width); - } + regs.q[floatReg] = val; return NoFault; } void FloatRegFile::serialize(std::ostream &os) { - uint8_t *float_reg = (uint8_t*)regSpace; - SERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); + SERIALIZE_ARRAY(regs.q, NumFloatRegs); } void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) { - uint8_t *float_reg = (uint8_t*)regSpace; - UNSERIALIZE_ARRAY(float_reg, - SingleWidth / 8 * NumFloatRegs); + UNSERIALIZE_ARRAY(regs.q, NumFloatRegs); } diff --git a/src/arch/sparc/floatregfile.hh b/src/arch/sparc/floatregfile.hh index 265e71b4a..d1ac39842 100644 --- a/src/arch/sparc/floatregfile.hh +++ b/src/arch/sparc/floatregfile.hh @@ -45,37 +45,25 @@ namespace SparcISA const int NumFloatArchRegs = 64; const int NumFloatRegs = 64; - typedef float float32_t; - typedef double float64_t; - //FIXME long double refers to a 10 byte float, rather than a - //16 byte float as required. This data type may have to be emulated. - typedef double float128_t; - class FloatRegFile { - public: - static const int SingleWidth = 32; - static const int DoubleWidth = 64; - static const int QuadWidth = 128; - protected: - - //Since the floating point registers overlap each other, - //A generic storage space is used. The float to be returned is - //pulled from the appropriate section of this region. - char regSpace[(SingleWidth / 8) * NumFloatRegs]; + union { + uint32_t q[NumFloatRegs]; + float s[NumFloatRegs]; + } regs; public: void clear(); - FloatReg readReg(int floatReg, int width); + FloatReg readReg(int floatReg); - FloatRegBits readRegBits(int floatReg, int width); + FloatRegBits readRegBits(int floatReg); - Fault setReg(int floatReg, const FloatReg &val, int width); + Fault setReg(int floatReg, const FloatReg &val); - Fault setRegBits(int floatReg, const FloatRegBits &val, int width); + Fault setRegBits(int floatReg, const FloatRegBits &val); void serialize(std::ostream &os); diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 1daa43818..287516f9a 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -74,49 +74,24 @@ void RegFile::clear() intRegFile.clear(); } -FloatReg RegFile::readFloatReg(int floatReg, int width) -{ - return floatRegFile.readReg(floatReg, width); -} - FloatReg RegFile::readFloatReg(int floatReg) { - //Use the "natural" width of a single float - return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg, int width) -{ - return floatRegFile.readRegBits(floatReg, width); + return floatRegFile.readReg(floatReg); } FloatRegBits RegFile::readFloatRegBits(int floatReg) { - //Use the "natural" width of a single float - return floatRegFile.readRegBits(floatReg, - FloatRegFile::SingleWidth); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width) -{ - floatRegFile.setReg(floatReg, val, width); + return floatRegFile.readRegBits(floatReg); } void RegFile::setFloatReg(int floatReg, const FloatReg &val) { - //Use the "natural" width of a single float - setFloatReg(floatReg, val, FloatRegFile::SingleWidth); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width) -{ - floatRegFile.setRegBits(floatReg, val, width); + floatRegFile.setReg(floatReg, val); } void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) { - //Use the "natural" width of a single float - floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth); + floatRegFile.setRegBits(floatReg, val); } IntReg RegFile::readIntReg(int intReg) diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 2333d9da5..a9d9be200 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -70,20 +70,12 @@ namespace SparcISA void clear(); - FloatReg readFloatReg(int floatReg, int width); - FloatReg readFloatReg(int floatReg); - FloatRegBits readFloatRegBits(int floatReg, int width); - FloatRegBits readFloatRegBits(int floatReg); - void setFloatReg(int floatReg, const FloatReg &val, int width); - void setFloatReg(int floatReg, const FloatReg &val); - void setFloatRegBits(int floatReg, const FloatRegBits &val, int width); - void setFloatRegBits(int floatReg, const FloatRegBits &val); IntReg readIntReg(int intReg); diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh index 501e2e8cb..c7ece9dfa 100644 --- a/src/arch/sparc/types.hh +++ b/src/arch/sparc/types.hh @@ -42,8 +42,8 @@ namespace SparcISA typedef uint64_t IntReg; typedef Twin64_t LargestRead; typedef uint64_t MiscReg; - typedef double FloatReg; - typedef uint64_t FloatRegBits; + typedef float FloatReg; + typedef uint32_t FloatRegBits; typedef union { IntReg intReg; -- cgit v1.2.3 From 0cb180ea0dcece9157ad71b4136d557c2dbcf209 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Eliminate the ISA defined floating point register file. --- src/arch/sparc/SConscript | 1 - src/arch/sparc/floatregfile.cc | 80 ------------------------------------------ src/arch/sparc/floatregfile.hh | 74 -------------------------------------- src/arch/sparc/regfile.cc | 23 ------------ src/arch/sparc/regfile.hh | 10 ------ src/arch/sparc/sparc_traits.hh | 3 +- 6 files changed, 2 insertions(+), 189 deletions(-) delete mode 100644 src/arch/sparc/floatregfile.cc delete mode 100644 src/arch/sparc/floatregfile.hh (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index eb0d21598..2b10951d9 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -34,7 +34,6 @@ Import('*') if env['TARGET_ISA'] == 'sparc': Source('asi.cc') Source('faults.cc') - Source('floatregfile.cc') Source('intregfile.cc') Source('isa.cc') Source('miscregfile.cc') diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc deleted file mode 100644 index 6fdc36489..000000000 --- a/src/arch/sparc/floatregfile.cc +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/floatregfile.hh" -#include "base/trace.hh" -#include "sim/byteswap.hh" -#include "sim/serialize.hh" - -#include - -using namespace SparcISA; -using namespace std; - -class Checkpoint; - -void FloatRegFile::clear() -{ - memset(regs.q, 0, sizeof(regs.q)); -} - -FloatReg FloatRegFile::readReg(int floatReg) -{ - return regs.s[floatReg]; -} - -FloatRegBits FloatRegFile::readRegBits(int floatReg) -{ - return regs.q[floatReg]; -} - -Fault FloatRegFile::setReg(int floatReg, const FloatReg &val) -{ - regs.s[floatReg] = val; - return NoFault; -} - -Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val) -{ - regs.q[floatReg] = val; - return NoFault; -} - -void FloatRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs.q, NumFloatRegs); -} - -void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs.q, NumFloatRegs); -} - diff --git a/src/arch/sparc/floatregfile.hh b/src/arch/sparc/floatregfile.hh deleted file mode 100644 index d1ac39842..000000000 --- a/src/arch/sparc/floatregfile.hh +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_SPARC_FLOATREGFILE_HH__ -#define __ARCH_SPARC_FLOATREGFILE_HH__ - -#include "arch/sparc/faults.hh" -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/types.hh" - -#include - -class Checkpoint; - -namespace SparcISA -{ - const int NumFloatArchRegs = 64; - const int NumFloatRegs = 64; - - class FloatRegFile - { - protected: - union { - uint32_t q[NumFloatRegs]; - float s[NumFloatRegs]; - } regs; - - public: - - void clear(); - - FloatReg readReg(int floatReg); - - FloatRegBits readRegBits(int floatReg); - - Fault setReg(int floatReg, const FloatReg &val); - - Fault setRegBits(int floatReg, const FloatRegBits &val); - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - }; -} - -#endif diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 287516f9a..83a3dbcc2 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -70,30 +70,9 @@ void RegFile::setNextNPC(Addr val) void RegFile::clear() { - floatRegFile.clear(); intRegFile.clear(); } -FloatReg RegFile::readFloatReg(int floatReg) -{ - return floatRegFile.readReg(floatReg); -} - -FloatRegBits RegFile::readFloatRegBits(int floatReg) -{ - return floatRegFile.readRegBits(floatReg); -} - -void RegFile::setFloatReg(int floatReg, const FloatReg &val) -{ - floatRegFile.setReg(floatReg, val); -} - -void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val) -{ - floatRegFile.setRegBits(floatReg, val); -} - IntReg RegFile::readIntReg(int intReg) { return intRegFile.readReg(intReg); @@ -108,7 +87,6 @@ void RegFile::serialize(EventManager *em, ostream &os) { intRegFile.serialize(os); - floatRegFile.serialize(os); SERIALIZE_SCALAR(pc); SERIALIZE_SCALAR(npc); SERIALIZE_SCALAR(nnpc); @@ -118,7 +96,6 @@ void RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) { intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); UNSERIALIZE_SCALAR(pc); UNSERIALIZE_SCALAR(npc); UNSERIALIZE_SCALAR(nnpc); diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index a9d9be200..c28a5274f 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -34,7 +34,6 @@ #include -#include "arch/sparc/floatregfile.hh" #include "arch/sparc/intregfile.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/miscregfile.hh" @@ -64,20 +63,11 @@ namespace SparcISA protected: IntRegFile intRegFile; // integer register file - FloatRegFile floatRegFile; // floating point register file public: void clear(); - FloatReg readFloatReg(int floatReg); - - FloatRegBits readFloatRegBits(int floatReg); - - void setFloatReg(int floatReg, const FloatReg &val); - - void setFloatRegBits(int floatReg, const FloatRegBits &val); - IntReg readIntReg(int intReg); void setIntReg(int intReg, const IntReg &val); diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh index e154ba274..b8e3c2aef 100644 --- a/src/arch/sparc/sparc_traits.hh +++ b/src/arch/sparc/sparc_traits.hh @@ -49,7 +49,8 @@ namespace SparcISA // const int NumIntRegs = // NumRegularIntRegs + // NumMicroIntRegs; -// const int NumFloatRegs = 64; + const int NumFloatRegs = 64; + const int NumFloatArchRegs = NumFloatRegs; // const int NumMiscRegs = 40; } -- cgit v1.2.3 From a480ba00b96f4c2e872f5a01bfa1782500f1066e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Eliminate the ISA defined integer register file. --- src/arch/sparc/SConscript | 1 - src/arch/sparc/intregfile.cc | 80 -------------------------------------------- src/arch/sparc/intregfile.hh | 29 +--------------- src/arch/sparc/predecoder.hh | 1 + src/arch/sparc/regfile.cc | 17 ---------- src/arch/sparc/regfile.hh | 10 ++---- 6 files changed, 4 insertions(+), 134 deletions(-) delete mode 100644 src/arch/sparc/intregfile.cc (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 2b10951d9..cfc03b718 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -34,7 +34,6 @@ Import('*') if env['TARGET_ISA'] == 'sparc': Source('asi.cc') Source('faults.cc') - Source('intregfile.cc') Source('isa.cc') Source('miscregfile.cc') Source('pagetable.cc') diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc deleted file mode 100644 index 54c30d1cc..000000000 --- a/src/arch/sparc/intregfile.cc +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/intregfile.hh" -#include "base/trace.hh" -#include "base/misc.hh" -#include "sim/serialize.hh" - -#include - -using namespace SparcISA; -using namespace std; - -class Checkpoint; - -void IntRegFile::clear() -{ - memset(regs, 0, sizeof(IntReg) * NumIntRegs); -} - -IntRegFile::IntRegFile() -{ - clear(); -} - -IntReg IntRegFile::readReg(int intReg) -{ - DPRINTF(IntRegs, "Read register %d = 0x%x\n", intReg, regs[intReg]); - return regs[intReg]; -} - -void IntRegFile::setReg(int intReg, const IntReg &val) -{ - if(intReg) - { - DPRINTF(IntRegs, "Wrote register %d = 0x%x\n", intReg, val); - regs[intReg] = val; - } - return; -} - -void IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); - SERIALIZE_ARRAY(microRegs, NumMicroIntRegs); -} - -void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); - UNSERIALIZE_ARRAY(microRegs, NumMicroIntRegs); -} diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh index f669f6b0d..0165fca10 100644 --- a/src/arch/sparc/intregfile.hh +++ b/src/arch/sparc/intregfile.hh @@ -32,39 +32,12 @@ #ifndef __ARCH_SPARC_INTREGFILE_HH__ #define __ARCH_SPARC_INTREGFILE_HH__ -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/types.hh" -#include "base/bitfield.hh" - -#include - -class Checkpoint; +#include "arch/sparc/sparc_traits.hh" namespace SparcISA { const int NumIntArchRegs = 32; const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; - - class IntRegFile - { - protected: - IntReg microRegs[NumMicroIntRegs]; - IntReg regs[NumIntRegs]; - - public: - - void clear(); - - IntRegFile(); - - IntReg readReg(int intReg); - - void setReg(int intReg, const IntReg &val); - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - }; } #endif diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 7775e858e..137e91fbd 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -32,6 +32,7 @@ #define __ARCH_SPARC_PREDECODER_HH__ #include "arch/sparc/types.hh" +#include "base/bitfield.hh" #include "base/misc.hh" #include "base/types.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 83a3dbcc2..e48bb07fe 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -68,25 +68,9 @@ void RegFile::setNextNPC(Addr val) nnpc = val; } -void RegFile::clear() -{ - intRegFile.clear(); -} - -IntReg RegFile::readIntReg(int intReg) -{ - return intRegFile.readReg(intReg); -} - -void RegFile::setIntReg(int intReg, const IntReg &val) -{ - intRegFile.setReg(intReg, val); -} - void RegFile::serialize(EventManager *em, ostream &os) { - intRegFile.serialize(os); SERIALIZE_SCALAR(pc); SERIALIZE_SCALAR(npc); SERIALIZE_SCALAR(nnpc); @@ -95,7 +79,6 @@ RegFile::serialize(EventManager *em, ostream &os) void RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) { - intRegFile.unserialize(cp, section); UNSERIALIZE_SCALAR(pc); UNSERIALIZE_SCALAR(npc); UNSERIALIZE_SCALAR(nnpc); diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index c28a5274f..c3c53a414 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -61,16 +61,10 @@ namespace SparcISA Addr readNextNPC(); void setNextNPC(Addr val); - protected: - IntRegFile intRegFile; // integer register file - public: - void clear(); - - IntReg readIntReg(int intReg); - - void setIntReg(int intReg, const IntReg &val); + void clear() + {} void serialize(EventManager *em, std::ostream &os); void unserialize(EventManager *em, Checkpoint *cp, -- cgit v1.2.3 From faa6ebebe1121170778d005b384a21ce6da10308 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: SPARC: Phase out SPARC's intregfile.hh. --- src/arch/sparc/interrupts.hh | 1 + src/arch/sparc/intregfile.hh | 43 ------------------------------------------- src/arch/sparc/predecoder.hh | 1 + src/arch/sparc/process.cc | 1 + src/arch/sparc/regfile.cc | 1 + src/arch/sparc/regfile.hh | 10 +++++++--- src/arch/sparc/utility.hh | 1 + 7 files changed, 12 insertions(+), 46 deletions(-) delete mode 100644 src/arch/sparc/intregfile.hh (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index ec930e2b0..712397602 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -34,6 +34,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/miscregfile.hh" #include "cpu/thread_context.hh" #include "params/SparcInterrupts.hh" #include "sim/sim_object.hh" diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh deleted file mode 100644 index 0165fca10..000000000 --- a/src/arch/sparc/intregfile.hh +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_SPARC_INTREGFILE_HH__ -#define __ARCH_SPARC_INTREGFILE_HH__ - -#include "arch/sparc/sparc_traits.hh" - -namespace SparcISA -{ - const int NumIntArchRegs = 32; - const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; -} - -#endif diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 137e91fbd..8c2ab1efd 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -31,6 +31,7 @@ #ifndef __ARCH_SPARC_PREDECODER_HH__ #define __ARCH_SPARC_PREDECODER_HH__ +#include "arch/sparc/miscregfile.hh" #include "arch/sparc/types.hh" #include "base/bitfield.hh" #include "base/misc.hh" diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 533e385b3..b35190d1b 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -32,6 +32,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/handlers.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/miscregfile.hh" #include "arch/sparc/process.hh" #include "arch/sparc/types.hh" #include "base/loader/object_file.hh" diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index e48bb07fe..574deab6c 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -30,6 +30,7 @@ */ #include "arch/sparc/regfile.hh" +#include "arch/sparc/miscregfile.hh" #include "cpu/thread_context.hh" class Checkpoint; diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index c3c53a414..b468d568b 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -34,16 +34,20 @@ #include -#include "arch/sparc/intregfile.hh" -#include "arch/sparc/isa_traits.hh" #include "arch/sparc/miscregfile.hh" -#include "arch/sparc/types.hh" +#include "arch/sparc/sparc_traits.hh" #include "base/types.hh" +#include "sim/serialize.hh" class Checkpoint; +class EventManager; +class ThreadContext; namespace SparcISA { + const int NumIntArchRegs = 32; + const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; + class RegFile { protected: diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 4ad8950b1..c0c3756f5 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -33,6 +33,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/miscregfile.hh" #include "arch/sparc/tlb.hh" #include "base/misc.hh" #include "base/bitfield.hh" -- cgit v1.2.3 From 43345bff6c4ee2fd5a35760776898eefa690329e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:21 -0700 Subject: Registers: Move the PCs out of the ISAs and into the CPUs. --- src/arch/sparc/regfile.cc | 50 ----------------------------------------------- src/arch/sparc/regfile.hh | 26 +++++------------------- 2 files changed, 5 insertions(+), 71 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 574deab6c..28ffc57aa 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -33,57 +33,7 @@ #include "arch/sparc/miscregfile.hh" #include "cpu/thread_context.hh" -class Checkpoint; - using namespace SparcISA; -using namespace std; - -//RegFile class methods -Addr RegFile::readPC() -{ - return pc; -} - -void RegFile::setPC(Addr val) -{ - pc = val; -} - -Addr RegFile::readNextPC() -{ - return npc; -} - -void RegFile::setNextPC(Addr val) -{ - npc = val; -} - -Addr RegFile::readNextNPC() -{ - return nnpc; -} - -void RegFile::setNextNPC(Addr val) -{ - nnpc = val; -} - -void -RegFile::serialize(EventManager *em, ostream &os) -{ - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) -{ - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); -} void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) { diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index b468d568b..b0c2aabbd 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -32,12 +32,11 @@ #ifndef __ARCH_SPARC_REGFILE_HH__ #define __ARCH_SPARC_REGFILE_HH__ +#include #include #include "arch/sparc/miscregfile.hh" #include "arch/sparc/sparc_traits.hh" -#include "base/types.hh" -#include "sim/serialize.hh" class Checkpoint; class EventManager; @@ -50,31 +49,16 @@ namespace SparcISA class RegFile { - protected: - Addr pc; // Program Counter - Addr npc; // Next Program Counter - Addr nnpc; - - public: - Addr readPC(); - void setPC(Addr val); - - Addr readNextPC(); - void setNextPC(Addr val); - - Addr readNextNPC(); - void setNextNPC(Addr val); - public: void clear() {} - void serialize(EventManager *em, std::ostream &os); + void serialize(EventManager *em, std::ostream &os) + {} void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - - public: + const std::string §ion) + {} }; void copyRegs(ThreadContext *src, ThreadContext *dest); -- cgit v1.2.3 From 5c37d10624e0f9a9568f1eb1527832c55addba59 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:21 -0700 Subject: Registers: Eliminate the ISA defined RegFile class. --- src/arch/sparc/isa_traits.hh | 2 -- src/arch/sparc/regfile.hh | 14 -------------- 2 files changed, 16 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 00dadcf3d..407602f90 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -44,8 +44,6 @@ namespace BigEndianGuest {} namespace SparcISA { - class RegFile; - const int MachineBytes = 8; //This makes sure the big endian versions of certain functions are used. diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index b0c2aabbd..28885271f 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -47,20 +47,6 @@ namespace SparcISA const int NumIntArchRegs = 32; const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; - class RegFile - { - public: - - void clear() - {} - - void serialize(EventManager *em, std::ostream &os) - {} - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion) - {} - }; - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); -- cgit v1.2.3 From b398b8ff1ba7e181e010afd6219074cf6f683820 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:21 -0700 Subject: Registers: Add a registers.hh file as an ISA switched header. This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh --- src/arch/sparc/SConscript | 1 - src/arch/sparc/isa/includes.isa | 2 +- src/arch/sparc/isa_traits.hh | 20 ---- src/arch/sparc/linux/process.cc | 2 +- src/arch/sparc/miscregfile.hh | 121 +----------------------- src/arch/sparc/miscregs.hh | 159 +++++++++++++++++++++++++++++++ src/arch/sparc/regfile.cc | 190 -------------------------------------- src/arch/sparc/regfile.hh | 56 ----------- src/arch/sparc/registers.hh | 80 ++++++++++++++++ src/arch/sparc/solaris/process.cc | 2 +- src/arch/sparc/types.hh | 12 --- src/arch/sparc/utility.cc | 155 +++++++++++++++++++++++++++++++ src/arch/sparc/utility.hh | 4 + 13 files changed, 403 insertions(+), 401 deletions(-) create mode 100644 src/arch/sparc/miscregs.hh delete mode 100644 src/arch/sparc/regfile.cc delete mode 100644 src/arch/sparc/regfile.hh create mode 100644 src/arch/sparc/registers.hh (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index cfc03b718..5dcadc143 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -37,7 +37,6 @@ if env['TARGET_ISA'] == 'sparc': Source('isa.cc') Source('miscregfile.cc') Source('pagetable.cc') - Source('regfile.cc') Source('remote_gdb.cc') Source('tlb.cc') Source('utility.cc') diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 135bd58c3..bc9273ad3 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -40,7 +40,7 @@ output header {{ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/condcodes.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 407602f90..2af624d39 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -33,7 +33,6 @@ #define __ARCH_SPARC_ISA_TRAITS_HH__ #include "arch/sparc/types.hh" -#include "arch/sparc/max_inst_regs.hh" #include "arch/sparc/sparc_traits.hh" #include "base/types.hh" #include "config/full_system.hh" @@ -48,8 +47,6 @@ namespace SparcISA //This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; - using SparcISAInst::MaxInstSrcRegs; - using SparcISAInst::MaxInstDestRegs; // SPARC has a delay slot #define ISA_HAS_DELAY_SLOT 1 @@ -57,23 +54,6 @@ namespace SparcISA // SPARC NOP (sethi %(hi(0), g0) const MachInst NoopMachInst = 0x01000000; - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - FP_Base_DepTag = 32*3+9, - Ctrl_Base_DepTag = FP_Base_DepTag + 64 - }; - - // semantically meaningful register indices - const int ZeroReg = 0; // architecturally meaningful - // the rest of these depend on the ABI - const int ReturnAddressReg = 31; // post call, precall is 15 - const int ReturnValueReg = 8; // Post return, 24 is pre-return. - const int StackPointerReg = 14; - const int FramePointerReg = 30; - - // Some OS syscall use a second register (o1) to return a second value - const int SyscallPseudoReturnReg = 9; - //8K. This value is implmentation specific; and should probably //be somewhere else. const int LogVMPageSize = 13; diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index 28aa1e50c..b39508386 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -32,7 +32,7 @@ #include "arch/sparc/isa_traits.hh" #include "arch/sparc/linux/process.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 9eff7fcac..c6ba27b93 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -34,6 +34,8 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/miscregs.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" #include "cpu/cpuevent.hh" @@ -43,125 +45,6 @@ class Checkpoint; namespace SparcISA { - enum MiscRegIndex - { - /** Ancillary State Registers */ -// MISCREG_Y, -// MISCREG_CCR, - MISCREG_ASI, - MISCREG_TICK, - MISCREG_FPRS, - MISCREG_PCR, - MISCREG_PIC, - MISCREG_GSR, - MISCREG_SOFTINT_SET, - MISCREG_SOFTINT_CLR, - MISCREG_SOFTINT, /* 10 */ - MISCREG_TICK_CMPR, - MISCREG_STICK, - MISCREG_STICK_CMPR, - - /** Privilged Registers */ - MISCREG_TPC, - MISCREG_TNPC, - MISCREG_TSTATE, - MISCREG_TT, - MISCREG_PRIVTICK, - MISCREG_TBA, - MISCREG_PSTATE, /* 20 */ - MISCREG_TL, - MISCREG_PIL, - MISCREG_CWP, -// MISCREG_CANSAVE, -// MISCREG_CANRESTORE, -// MISCREG_CLEANWIN, -// MISCREG_OTHERWIN, -// MISCREG_WSTATE, - MISCREG_GL, - - /** Hyper privileged registers */ - MISCREG_HPSTATE, /* 30 */ - MISCREG_HTSTATE, - MISCREG_HINTP, - MISCREG_HTBA, - MISCREG_HVER, - MISCREG_STRAND_STS_REG, - MISCREG_HSTICK_CMPR, - - /** Floating Point Status Register */ - MISCREG_FSR, - - /** MMU Internal Registers */ - MISCREG_MMU_P_CONTEXT, - MISCREG_MMU_S_CONTEXT, /* 40 */ - MISCREG_MMU_PART_ID, - MISCREG_MMU_LSU_CTRL, - - /** Scratchpad regiscers **/ - MISCREG_SCRATCHPAD_R0, /* 60 */ - MISCREG_SCRATCHPAD_R1, - MISCREG_SCRATCHPAD_R2, - MISCREG_SCRATCHPAD_R3, - MISCREG_SCRATCHPAD_R4, - MISCREG_SCRATCHPAD_R5, - MISCREG_SCRATCHPAD_R6, - MISCREG_SCRATCHPAD_R7, - - /* CPU Queue Registers */ - MISCREG_QUEUE_CPU_MONDO_HEAD, - MISCREG_QUEUE_CPU_MONDO_TAIL, - MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ - MISCREG_QUEUE_DEV_MONDO_TAIL, - MISCREG_QUEUE_RES_ERROR_HEAD, - MISCREG_QUEUE_RES_ERROR_TAIL, - MISCREG_QUEUE_NRES_ERROR_HEAD, - MISCREG_QUEUE_NRES_ERROR_TAIL, - - /* All the data for the TLB packed up in one register. */ - MISCREG_TLB_DATA, - MISCREG_NUMMISCREGS - }; - - struct HPSTATE { - const static uint64_t id = 0x800; // this impl. dependent (id) field m - const static uint64_t ibe = 0x400; - const static uint64_t red = 0x20; - const static uint64_t hpriv = 0x4; - const static uint64_t tlz = 0x1; - }; - - - struct PSTATE { - const static int cle = 0x200; - const static int tle = 0x100; - const static int mm = 0xC0; - const static int pef = 0x10; - const static int am = 0x8; - const static int priv = 0x4; - const static int ie = 0x2; - }; - - struct STS { - const static int st_idle = 0x00; - const static int st_wait = 0x01; - const static int st_halt = 0x02; - const static int st_run = 0x05; - const static int st_spec_run = 0x07; - const static int st_spec_rdy = 0x13; - const static int st_ready = 0x19; - const static int active = 0x01; - const static int speculative = 0x04; - const static int shft_id = 8; - const static int shft_fsm0 = 31; - const static int shft_fsm1 = 26; - const static int shft_fsm2 = 21; - const static int shft_fsm3 = 16; - }; - - - const int NumMiscArchRegs = MISCREG_NUMMISCREGS; - const int NumMiscRegs = MISCREG_NUMMISCREGS; - // The control registers, broken out into fields class MiscRegFile { diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh new file mode 100644 index 000000000..f7fff6ee0 --- /dev/null +++ b/src/arch/sparc/miscregs.hh @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi + */ + +#ifndef __ARCH_SPARC_MISCREGS_HH__ +#define __ARCH_SPARC_MISCREGS_HH__ + +#include "base/types.hh" + +namespace SparcISA +{ + enum MiscRegIndex + { + /** Ancillary State Registers */ +// MISCREG_Y, +// MISCREG_CCR, + MISCREG_ASI, + MISCREG_TICK, + MISCREG_FPRS, + MISCREG_PCR, + MISCREG_PIC, + MISCREG_GSR, + MISCREG_SOFTINT_SET, + MISCREG_SOFTINT_CLR, + MISCREG_SOFTINT, /* 10 */ + MISCREG_TICK_CMPR, + MISCREG_STICK, + MISCREG_STICK_CMPR, + + /** Privilged Registers */ + MISCREG_TPC, + MISCREG_TNPC, + MISCREG_TSTATE, + MISCREG_TT, + MISCREG_PRIVTICK, + MISCREG_TBA, + MISCREG_PSTATE, /* 20 */ + MISCREG_TL, + MISCREG_PIL, + MISCREG_CWP, +// MISCREG_CANSAVE, +// MISCREG_CANRESTORE, +// MISCREG_CLEANWIN, +// MISCREG_OTHERWIN, +// MISCREG_WSTATE, + MISCREG_GL, + + /** Hyper privileged registers */ + MISCREG_HPSTATE, /* 30 */ + MISCREG_HTSTATE, + MISCREG_HINTP, + MISCREG_HTBA, + MISCREG_HVER, + MISCREG_STRAND_STS_REG, + MISCREG_HSTICK_CMPR, + + /** Floating Point Status Register */ + MISCREG_FSR, + + /** MMU Internal Registers */ + MISCREG_MMU_P_CONTEXT, + MISCREG_MMU_S_CONTEXT, /* 40 */ + MISCREG_MMU_PART_ID, + MISCREG_MMU_LSU_CTRL, + + /** Scratchpad regiscers **/ + MISCREG_SCRATCHPAD_R0, /* 60 */ + MISCREG_SCRATCHPAD_R1, + MISCREG_SCRATCHPAD_R2, + MISCREG_SCRATCHPAD_R3, + MISCREG_SCRATCHPAD_R4, + MISCREG_SCRATCHPAD_R5, + MISCREG_SCRATCHPAD_R6, + MISCREG_SCRATCHPAD_R7, + + /* CPU Queue Registers */ + MISCREG_QUEUE_CPU_MONDO_HEAD, + MISCREG_QUEUE_CPU_MONDO_TAIL, + MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ + MISCREG_QUEUE_DEV_MONDO_TAIL, + MISCREG_QUEUE_RES_ERROR_HEAD, + MISCREG_QUEUE_RES_ERROR_TAIL, + MISCREG_QUEUE_NRES_ERROR_HEAD, + MISCREG_QUEUE_NRES_ERROR_TAIL, + + /* All the data for the TLB packed up in one register. */ + MISCREG_TLB_DATA, + MISCREG_NUMMISCREGS + }; + + struct HPSTATE { + const static uint64_t id = 0x800; // this impl. dependent (id) field m + const static uint64_t ibe = 0x400; + const static uint64_t red = 0x20; + const static uint64_t hpriv = 0x4; + const static uint64_t tlz = 0x1; + }; + + + struct PSTATE { + const static int cle = 0x200; + const static int tle = 0x100; + const static int mm = 0xC0; + const static int pef = 0x10; + const static int am = 0x8; + const static int priv = 0x4; + const static int ie = 0x2; + }; + + struct STS { + const static int st_idle = 0x00; + const static int st_wait = 0x01; + const static int st_halt = 0x02; + const static int st_run = 0x05; + const static int st_spec_run = 0x07; + const static int st_spec_rdy = 0x13; + const static int st_ready = 0x19; + const static int active = 0x01; + const static int speculative = 0x04; + const static int shft_id = 8; + const static int shft_fsm0 = 31; + const static int shft_fsm1 = 26; + const static int shft_fsm2 = 21; + const static int shft_fsm3 = 16; + }; + + + const int NumMiscArchRegs = MISCREG_NUMMISCREGS; + const int NumMiscRegs = MISCREG_NUMMISCREGS; +} + +#endif diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc deleted file mode 100644 index 28ffc57aa..000000000 --- a/src/arch/sparc/regfile.cc +++ /dev/null @@ -1,190 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/regfile.hh" -#include "arch/sparc/miscregfile.hh" -#include "cpu/thread_context.hh" - -using namespace SparcISA; - -void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - - uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); - - // Read all the trap level dependent registers and save them off - for(int i = 1; i <= MaxTL; i++) - { - src->setMiscRegNoEffect(MISCREG_TL, i); - dest->setMiscRegNoEffect(MISCREG_TL, i); - - dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); - dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); - dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); - dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); - } - - // Save off the traplevel - dest->setMiscRegNoEffect(MISCREG_TL, tl); - src->setMiscRegNoEffect(MISCREG_TL, tl); - - - // ASRs -// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); -// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); - dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); - dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); - dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); - dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); - dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); - dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); - dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); - - // Priv Registers - dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); - dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); - dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); - dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); - dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); -// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); -// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); -// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); -// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); -// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); - dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); - - // Hyperprivilged registers - dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); - dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); - dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); - dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, - src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); - dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, - src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); - - // FSR - dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); - - //Strand Status Register - dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, - src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); - - // MMU Registers - dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, - src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); - dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, - src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); - dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, - src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); - dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, - src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); - - // Scratchpad Registers - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); - dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, - src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); - - // Queue Registers - dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, - src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); - dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, - src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); -} - -void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - //First loop through the integer registers. - int old_gl = src->readMiscRegNoEffect(MISCREG_GL); - int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); - //Globals - for (int x = 0; x < MaxGL; ++x) { - src->setMiscRegNoEffect(MISCREG_GL, x); - dest->setMiscRegNoEffect(MISCREG_GL, x); - // Skip %g0 which is always zero. - for (int y = 1; y < 8; y++) - dest->setIntReg(y, src->readIntReg(y)); - } - //Locals and ins. Outs are all also ins. - for (int x = 0; x < NWindows; ++x) { - src->setMiscRegNoEffect(MISCREG_CWP, x); - dest->setMiscRegNoEffect(MISCREG_CWP, x); - for (int y = 16; y < 32; y++) - dest->setIntReg(y, src->readIntReg(y)); - } - //Microcode reg and pseudo int regs (misc regs in the integer regfile). - for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) - dest->setIntReg(y, src->readIntReg(y)); - - //Restore src's GL, CWP - src->setMiscRegNoEffect(MISCREG_GL, old_gl); - src->setMiscRegNoEffect(MISCREG_CWP, old_cwp); - - - // Then loop through the floating point registers. - for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { - dest->setFloatRegBits(i, src->readFloatRegBits(i)); - } - - // Copy misc. registers - copyMiscRegs(src, dest); - - - // Lastly copy PC/NPC - dest->setPC(src->readPC()); - dest->setNextPC(src->readNextPC()); - dest->setNextNPC(src->readNextNPC()); -} - diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh deleted file mode 100644 index 28885271f..000000000 --- a/src/arch/sparc/regfile.hh +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_SPARC_REGFILE_HH__ -#define __ARCH_SPARC_REGFILE_HH__ - -#include -#include - -#include "arch/sparc/miscregfile.hh" -#include "arch/sparc/sparc_traits.hh" - -class Checkpoint; -class EventManager; -class ThreadContext; - -namespace SparcISA -{ - const int NumIntArchRegs = 32; - const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; - - void copyRegs(ThreadContext *src, ThreadContext *dest); - - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - -} // namespace SparcISA - -#endif diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh new file mode 100644 index 000000000..639b7a487 --- /dev/null +++ b/src/arch/sparc/registers.hh @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi + */ + +#ifndef __ARCH_SPARC_REGISTERS_HH__ +#define __ARCH_SPARC_REGISTERS_HH__ + +#include "arch/sparc/max_inst_regs.hh" +#include "arch/sparc/miscregs.hh" +#include "arch/sparc/sparc_traits.hh" +#include "base/types.hh" + +namespace SparcISA +{ + using SparcISAInst::MaxInstSrcRegs; + using SparcISAInst::MaxInstDestRegs; + + typedef uint64_t IntReg; + typedef uint64_t MiscReg; + typedef float FloatReg; + typedef uint32_t FloatRegBits; + typedef union + { + IntReg intReg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + typedef uint16_t RegIndex; + + // These enumerate all the registers for dependence tracking. + enum DependenceTags { + FP_Base_DepTag = 32*3+9, + Ctrl_Base_DepTag = FP_Base_DepTag + 64 + }; + + // semantically meaningful register indices + const int ZeroReg = 0; // architecturally meaningful + // the rest of these depend on the ABI + const int ReturnAddressReg = 31; // post call, precall is 15 + const int ReturnValueReg = 8; // Post return, 24 is pre-return. + const int StackPointerReg = 14; + const int FramePointerReg = 30; + + // Some OS syscall use a second register (o1) to return a second value + const int SyscallPseudoReturnReg = 9; + + const int NumIntArchRegs = 32; + const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; + +} // namespace SparcISA + +#endif diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index 22924736b..eafb488df 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -30,7 +30,7 @@ #include "arch/sparc/isa_traits.hh" #include "arch/sparc/solaris/process.hh" -#include "arch/sparc/regfile.hh" +#include "arch/sparc/registers.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh index c7ece9dfa..70558ec6d 100644 --- a/src/arch/sparc/types.hh +++ b/src/arch/sparc/types.hh @@ -39,19 +39,7 @@ namespace SparcISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; - typedef uint64_t IntReg; typedef Twin64_t LargestRead; - typedef uint64_t MiscReg; - typedef float FloatReg; - typedef uint32_t FloatRegBits; - typedef union - { - IntReg intReg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - - typedef uint16_t RegIndex; struct CoreSpecific { int core_type; diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index d4cc286e6..9c9b833fe 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -61,4 +61,159 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) { M5_DUMMY_RETURN #endif } + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + + uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); + + // Read all the trap level dependent registers and save them off + for(int i = 1; i <= MaxTL; i++) + { + src->setMiscRegNoEffect(MISCREG_TL, i); + dest->setMiscRegNoEffect(MISCREG_TL, i); + + dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); + dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); + dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); + dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); + } + + // Save off the traplevel + dest->setMiscRegNoEffect(MISCREG_TL, tl); + src->setMiscRegNoEffect(MISCREG_TL, tl); + + + // ASRs +// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); +// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); + dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); + dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); + dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); + dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); + dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); + + // Priv Registers + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); + dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); + dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); + dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); +// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); +// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); +// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); +// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); +// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); + dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); + + // Hyperprivilged registers + dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); + dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); + dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); + dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, + src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); + + // FSR + dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); + + //Strand Status Register + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); + + // MMU Registers + dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, + src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); + dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, + src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); + + // Scratchpad Registers + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); + + // Queue Registers + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); +} + +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + //First loop through the integer registers. + int old_gl = src->readMiscRegNoEffect(MISCREG_GL); + int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); + //Globals + for (int x = 0; x < MaxGL; ++x) { + src->setMiscRegNoEffect(MISCREG_GL, x); + dest->setMiscRegNoEffect(MISCREG_GL, x); + // Skip %g0 which is always zero. + for (int y = 1; y < 8; y++) + dest->setIntReg(y, src->readIntReg(y)); + } + //Locals and ins. Outs are all also ins. + for (int x = 0; x < NWindows; ++x) { + src->setMiscRegNoEffect(MISCREG_CWP, x); + dest->setMiscRegNoEffect(MISCREG_CWP, x); + for (int y = 16; y < 32; y++) + dest->setIntReg(y, src->readIntReg(y)); + } + //Microcode reg and pseudo int regs (misc regs in the integer regfile). + for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) + dest->setIntReg(y, src->readIntReg(y)); + + //Restore src's GL, CWP + src->setMiscRegNoEffect(MISCREG_GL, old_gl); + src->setMiscRegNoEffect(MISCREG_CWP, old_cwp); + + + // Then loop through the floating point registers. + for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { + dest->setFloatRegBits(i, src->readFloatRegBits(i)); + } + + // Copy misc. registers + copyMiscRegs(src, dest); + + + // Lastly copy PC/NPC + dest->setPC(src->readPC()); + dest->setNextPC(src->readNextPC()); + dest->setNextNPC(src->readNextNPC()); +} } //namespace SPARC_ISA diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index c0c3756f5..551570723 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -116,6 +116,10 @@ namespace SparcISA #endif } + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + } // namespace SparcISA #endif -- cgit v1.2.3 From c9a27d85b9066489bf227f19d61ce5ddd1bc91c3 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:22 -0700 Subject: Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. --- src/arch/sparc/isa.hh | 11 ----------- src/arch/sparc/miscregfile.hh | 10 ---------- 2 files changed, 21 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 1dbfe7a28..bba578ef1 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -45,17 +45,6 @@ namespace SparcISA MiscRegFile miscRegFile; public: - - int instAsid() - { - return miscRegFile.getInstAsid(); - } - - int dataAsid() - { - return miscRegFile.getDataAsid(); - } - void clear(); MiscReg readMiscRegNoEffect(int miscReg); diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index c6ba27b93..36c309db2 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -158,16 +158,6 @@ namespace SparcISA void setReg(int miscReg, const MiscReg &val, ThreadContext * tc); - int getInstAsid() - { - return priContext | (uint32_t)partId << 13; - } - - int getDataAsid() - { - return priContext | (uint32_t)partId << 13; - } - void serialize(EventManager *em, std::ostream & os); void unserialize(EventManager *em, Checkpoint *cp, -- cgit v1.2.3 From 60d47aa5f9018bf29651ec33ae1f20793fcdc4eb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 9 Jul 2009 20:28:50 -0700 Subject: SPARC: Fold the MiscRegFile all the way into the ISA object. --- src/arch/sparc/SConscript | 1 - src/arch/sparc/interrupts.hh | 2 +- src/arch/sparc/isa.cc | 691 ++++++++++++++++++++++++++++++++++++++-- src/arch/sparc/isa.hh | 119 ++++++- src/arch/sparc/miscregfile.cc | 724 ------------------------------------------ src/arch/sparc/miscregfile.hh | 176 ---------- src/arch/sparc/predecoder.hh | 2 +- src/arch/sparc/process.cc | 2 +- src/arch/sparc/tlb.cc | 2 +- src/arch/sparc/ua2005.cc | 59 ++-- src/arch/sparc/utility.hh | 2 +- 11 files changed, 816 insertions(+), 964 deletions(-) delete mode 100644 src/arch/sparc/miscregfile.cc delete mode 100644 src/arch/sparc/miscregfile.hh (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 5dcadc143..86ccaa010 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -35,7 +35,6 @@ if env['TARGET_ISA'] == 'sparc': Source('asi.cc') Source('faults.cc') Source('isa.cc') - Source('miscregfile.cc') Source('pagetable.cc') Source('remote_gdb.cc') Source('tlb.cc') diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index 712397602..353521a39 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -34,7 +34,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "cpu/thread_context.hh" #include "params/SparcInterrupts.hh" #include "sim/sim_object.hh" diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 3aeeb14ab..61366937f 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -28,47 +28,706 @@ * Authors: Gabe Black */ +#include "arch/sparc/asi.hh" #include "arch/sparc/isa.hh" +#include "base/bitfield.hh" +#include "base/trace.hh" +#include "config/full_system.hh" +#include "cpu/base.hh" #include "cpu/thread_context.hh" namespace SparcISA { +enum RegMask +{ + PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12) +}; + void ISA::clear() { - miscRegFile.clear(); + //y = 0; + //ccr = 0; + asi = 0; + tick = ULL(1) << 63; + fprs = 0; + gsr = 0; + softint = 0; + tick_cmpr = 0; + stick = 0; + stick_cmpr = 0; + memset(tpc, 0, sizeof(tpc)); + memset(tnpc, 0, sizeof(tnpc)); + memset(tstate, 0, sizeof(tstate)); + memset(tt, 0, sizeof(tt)); + pstate = 0; + tl = 0; + pil = 0; + cwp = 0; + //cansave = 0; + //canrestore = 0; + //cleanwin = 0; + //otherwin = 0; + //wstate = 0; + gl = 0; + //In a T1, bit 11 is apparently always 1 + hpstate = (1 << 11); + memset(htstate, 0, sizeof(htstate)); + hintp = 0; + htba = 0; + hstick_cmpr = 0; + //This is set this way in Legion for some reason + strandStatusReg = 0x50000; + fsr = 0; + + priContext = 0; + secContext = 0; + partId = 0; + lsuCtrlReg = 0; + + memset(scratchPad, 0, sizeof(scratchPad)); +#if FULL_SYSTEM + tickCompare = NULL; + sTickCompare = NULL; + hSTickCompare = NULL; +#endif } MiscReg ISA::readMiscRegNoEffect(int miscReg) { - return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg); + + // The three miscRegs are moved up from the switch statement + // due to more frequent calls. + + if (miscReg == MISCREG_GL) + return gl; + if (miscReg == MISCREG_CWP) + return cwp; + if (miscReg == MISCREG_TLB_DATA) { + /* Package up all the data for the tlb: + * 6666555555555544444444443333333333222222222211111111110000000000 + * 3210987654321098765432109876543210987654321098765432109876543210 + * secContext | priContext | |tl|partid| |||||^hpriv + * ||||^red + * |||^priv + * ||^am + * |^lsuim + * ^lsudm + */ + return bits((uint64_t)hpstate,2,2) | + bits((uint64_t)hpstate,5,5) << 1 | + bits((uint64_t)pstate,3,2) << 2 | + bits((uint64_t)lsuCtrlReg,3,2) << 4 | + bits((uint64_t)partId,7,0) << 8 | + bits((uint64_t)tl,2,0) << 16 | + (uint64_t)priContext << 32 | + (uint64_t)secContext << 48; + } + + switch (miscReg) { + //case MISCREG_TLB_DATA: + // [original contents see above] + //case MISCREG_Y: + // return y; + //case MISCREG_CCR: + // return ccr; + case MISCREG_ASI: + return asi; + case MISCREG_FPRS: + return fprs; + case MISCREG_TICK: + return tick; + case MISCREG_PCR: + panic("PCR not implemented\n"); + case MISCREG_PIC: + panic("PIC not implemented\n"); + case MISCREG_GSR: + return gsr; + case MISCREG_SOFTINT: + return softint; + case MISCREG_TICK_CMPR: + return tick_cmpr; + case MISCREG_STICK: + return stick; + case MISCREG_STICK_CMPR: + return stick_cmpr; + + /** Privilged Registers */ + case MISCREG_TPC: + return tpc[tl-1]; + case MISCREG_TNPC: + return tnpc[tl-1]; + case MISCREG_TSTATE: + return tstate[tl-1]; + case MISCREG_TT: + return tt[tl-1]; + case MISCREG_PRIVTICK: + panic("Priviliged access to tick registers not implemented\n"); + case MISCREG_TBA: + return tba; + case MISCREG_PSTATE: + return pstate; + case MISCREG_TL: + return tl; + case MISCREG_PIL: + return pil; + //CWP, GL moved + //case MISCREG_CWP: + // return cwp; + //case MISCREG_CANSAVE: + // return cansave; + //case MISCREG_CANRESTORE: + // return canrestore; + //case MISCREG_CLEANWIN: + // return cleanwin; + //case MISCREG_OTHERWIN: + // return otherwin; + //case MISCREG_WSTATE: + // return wstate; + //case MISCREG_GL: + // return gl; + + /** Hyper privileged registers */ + case MISCREG_HPSTATE: + return hpstate; + case MISCREG_HTSTATE: + return htstate[tl-1]; + case MISCREG_HINTP: + return hintp; + case MISCREG_HTBA: + return htba; + case MISCREG_STRAND_STS_REG: + return strandStatusReg; + case MISCREG_HSTICK_CMPR: + return hstick_cmpr; + + /** Floating Point Status Register */ + case MISCREG_FSR: + DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr); + return fsr; + + case MISCREG_MMU_P_CONTEXT: + return priContext; + case MISCREG_MMU_S_CONTEXT: + return secContext; + case MISCREG_MMU_PART_ID: + return partId; + case MISCREG_MMU_LSU_CTRL: + return lsuCtrlReg; + + case MISCREG_SCRATCHPAD_R0: + return scratchPad[0]; + case MISCREG_SCRATCHPAD_R1: + return scratchPad[1]; + case MISCREG_SCRATCHPAD_R2: + return scratchPad[2]; + case MISCREG_SCRATCHPAD_R3: + return scratchPad[3]; + case MISCREG_SCRATCHPAD_R4: + return scratchPad[4]; + case MISCREG_SCRATCHPAD_R5: + return scratchPad[5]; + case MISCREG_SCRATCHPAD_R6: + return scratchPad[6]; + case MISCREG_SCRATCHPAD_R7: + return scratchPad[7]; + case MISCREG_QUEUE_CPU_MONDO_HEAD: + return cpu_mondo_head; + case MISCREG_QUEUE_CPU_MONDO_TAIL: + return cpu_mondo_tail; + case MISCREG_QUEUE_DEV_MONDO_HEAD: + return dev_mondo_head; + case MISCREG_QUEUE_DEV_MONDO_TAIL: + return dev_mondo_tail; + case MISCREG_QUEUE_RES_ERROR_HEAD: + return res_error_head; + case MISCREG_QUEUE_RES_ERROR_TAIL: + return res_error_tail; + case MISCREG_QUEUE_NRES_ERROR_HEAD: + return nres_error_head; + case MISCREG_QUEUE_NRES_ERROR_TAIL: + return nres_error_tail; + default: + panic("Miscellaneous register %d not implemented\n", miscReg); + } } MiscReg -ISA::readMiscReg(int miscReg, ThreadContext *tc) +ISA::readMiscReg(int miscReg, ThreadContext * tc) +{ + switch (miscReg) { + // tick and stick are aliased to each other in niagra + // well store the tick data in stick and the interrupt bit in tick + case MISCREG_STICK: + case MISCREG_TICK: + case MISCREG_PRIVTICK: + // I'm not sure why legion ignores the lowest two bits, but we'll go + // with it + // change from curCycle() to instCount() until we're done with legion + DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n", + tc->getCpuPtr()->instCount(), stick); + return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | + mbits(tick,63,63); + case MISCREG_FPRS: + // in legion if fp is enabled du and dl are set + return fprs | 0x3; + case MISCREG_PCR: + case MISCREG_PIC: + panic("Performance Instrumentation not impl\n"); + case MISCREG_SOFTINT_CLR: + case MISCREG_SOFTINT_SET: + panic("Can read from softint clr/set\n"); + case MISCREG_SOFTINT: + case MISCREG_TICK_CMPR: + case MISCREG_STICK_CMPR: + case MISCREG_HINTP: + case MISCREG_HTSTATE: + case MISCREG_HTBA: + case MISCREG_HVER: + case MISCREG_STRAND_STS_REG: + case MISCREG_HSTICK_CMPR: + case MISCREG_QUEUE_CPU_MONDO_HEAD: + case MISCREG_QUEUE_CPU_MONDO_TAIL: + case MISCREG_QUEUE_DEV_MONDO_HEAD: + case MISCREG_QUEUE_DEV_MONDO_TAIL: + case MISCREG_QUEUE_RES_ERROR_HEAD: + case MISCREG_QUEUE_RES_ERROR_TAIL: + case MISCREG_QUEUE_NRES_ERROR_HEAD: + case MISCREG_QUEUE_NRES_ERROR_TAIL: +#if FULL_SYSTEM + case MISCREG_HPSTATE: + return readFSReg(miscReg, tc); +#else + case MISCREG_HPSTATE: + //HPSTATE is special because because sometimes in privilege + //checks for instructions it will read HPSTATE to make sure + //the priv. level is ok So, we'll just have to tell it it + //isn't, instead of panicing. + return 0; + + panic("Accessing Fullsystem register %d in SE mode\n", miscReg); +#endif + + } + return readMiscRegNoEffect(miscReg); +} + +void +ISA::setMiscRegNoEffect(int miscReg, MiscReg val) +{ + switch (miscReg) { +// case MISCREG_Y: +// y = val; +// break; +// case MISCREG_CCR: +// ccr = val; +// break; + case MISCREG_ASI: + asi = val; + break; + case MISCREG_FPRS: + fprs = val; + break; + case MISCREG_TICK: + tick = val; + break; + case MISCREG_PCR: + panic("PCR not implemented\n"); + case MISCREG_PIC: + panic("PIC not implemented\n"); + case MISCREG_GSR: + gsr = val; + break; + case MISCREG_SOFTINT: + softint = val; + break; + case MISCREG_TICK_CMPR: + tick_cmpr = val; + break; + case MISCREG_STICK: + stick = val; + break; + case MISCREG_STICK_CMPR: + stick_cmpr = val; + break; + + /** Privilged Registers */ + case MISCREG_TPC: + tpc[tl-1] = val; + break; + case MISCREG_TNPC: + tnpc[tl-1] = val; + break; + case MISCREG_TSTATE: + tstate[tl-1] = val; + break; + case MISCREG_TT: + tt[tl-1] = val; + break; + case MISCREG_PRIVTICK: + panic("Priviliged access to tick regesiters not implemented\n"); + case MISCREG_TBA: + // clear lower 7 bits on writes. + tba = val & ULL(~0x7FFF); + break; + case MISCREG_PSTATE: + pstate = (val & PSTATE_MASK); + break; + case MISCREG_TL: + tl = val; + break; + case MISCREG_PIL: + pil = val; + break; + case MISCREG_CWP: + cwp = val; + break; +// case MISCREG_CANSAVE: +// cansave = val; +// break; +// case MISCREG_CANRESTORE: +// canrestore = val; +// break; +// case MISCREG_CLEANWIN: +// cleanwin = val; +// break; +// case MISCREG_OTHERWIN: +// otherwin = val; +// break; +// case MISCREG_WSTATE: +// wstate = val; +// break; + case MISCREG_GL: + gl = val; + break; + + /** Hyper privileged registers */ + case MISCREG_HPSTATE: + hpstate = val; + break; + case MISCREG_HTSTATE: + htstate[tl-1] = val; + break; + case MISCREG_HINTP: + hintp = val; + case MISCREG_HTBA: + htba = val; + break; + case MISCREG_STRAND_STS_REG: + strandStatusReg = val; + break; + case MISCREG_HSTICK_CMPR: + hstick_cmpr = val; + break; + + /** Floating Point Status Register */ + case MISCREG_FSR: + fsr = val; + DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr); + break; + + case MISCREG_MMU_P_CONTEXT: + priContext = val; + break; + case MISCREG_MMU_S_CONTEXT: + secContext = val; + break; + case MISCREG_MMU_PART_ID: + partId = val; + break; + case MISCREG_MMU_LSU_CTRL: + lsuCtrlReg = val; + break; + + case MISCREG_SCRATCHPAD_R0: + scratchPad[0] = val; + break; + case MISCREG_SCRATCHPAD_R1: + scratchPad[1] = val; + break; + case MISCREG_SCRATCHPAD_R2: + scratchPad[2] = val; + break; + case MISCREG_SCRATCHPAD_R3: + scratchPad[3] = val; + break; + case MISCREG_SCRATCHPAD_R4: + scratchPad[4] = val; + break; + case MISCREG_SCRATCHPAD_R5: + scratchPad[5] = val; + break; + case MISCREG_SCRATCHPAD_R6: + scratchPad[6] = val; + break; + case MISCREG_SCRATCHPAD_R7: + scratchPad[7] = val; + break; + case MISCREG_QUEUE_CPU_MONDO_HEAD: + cpu_mondo_head = val; + break; + case MISCREG_QUEUE_CPU_MONDO_TAIL: + cpu_mondo_tail = val; + break; + case MISCREG_QUEUE_DEV_MONDO_HEAD: + dev_mondo_head = val; + break; + case MISCREG_QUEUE_DEV_MONDO_TAIL: + dev_mondo_tail = val; + break; + case MISCREG_QUEUE_RES_ERROR_HEAD: + res_error_head = val; + break; + case MISCREG_QUEUE_RES_ERROR_TAIL: + res_error_tail = val; + break; + case MISCREG_QUEUE_NRES_ERROR_HEAD: + nres_error_head = val; + break; + case MISCREG_QUEUE_NRES_ERROR_TAIL: + nres_error_tail = val; + break; + default: + panic("Miscellaneous register %d not implemented\n", miscReg); + } +} + +void +ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) { - return miscRegFile.readReg((MiscRegIndex)miscReg, tc); + MiscReg new_val = val; + + switch (miscReg) { + case MISCREG_STICK: + case MISCREG_TICK: + // stick and tick are same thing on niagra + // use stick for offset and tick for holding intrrupt bit + stick = mbits(val,62,0) - tc->getCpuPtr()->instCount(); + tick = mbits(val,63,63); + DPRINTF(Timer, "Writing TICK=%#X\n", val); + break; + case MISCREG_FPRS: + //Configure the fpu based on the fprs + break; + case MISCREG_PCR: + //Set up performance counting based on pcr value + break; + case MISCREG_PSTATE: + pstate = val & PSTATE_MASK; + return; + case MISCREG_TL: + tl = val; +#if FULL_SYSTEM + if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) + tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); + else + tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); +#endif + return; + case MISCREG_CWP: + new_val = val >= NWindows ? NWindows - 1 : val; + if (val >= NWindows) + new_val = NWindows - 1; + break; + case MISCREG_GL: + break; + case MISCREG_PIL: + case MISCREG_SOFTINT: + case MISCREG_SOFTINT_SET: + case MISCREG_SOFTINT_CLR: + case MISCREG_TICK_CMPR: + case MISCREG_STICK_CMPR: + case MISCREG_HINTP: + case MISCREG_HTSTATE: + case MISCREG_HTBA: + case MISCREG_HVER: + case MISCREG_STRAND_STS_REG: + case MISCREG_HSTICK_CMPR: + case MISCREG_QUEUE_CPU_MONDO_HEAD: + case MISCREG_QUEUE_CPU_MONDO_TAIL: + case MISCREG_QUEUE_DEV_MONDO_HEAD: + case MISCREG_QUEUE_DEV_MONDO_TAIL: + case MISCREG_QUEUE_RES_ERROR_HEAD: + case MISCREG_QUEUE_RES_ERROR_TAIL: + case MISCREG_QUEUE_NRES_ERROR_HEAD: + case MISCREG_QUEUE_NRES_ERROR_TAIL: +#if FULL_SYSTEM + case MISCREG_HPSTATE: + setFSReg(miscReg, val, tc); + return; +#else + case MISCREG_HPSTATE: + //HPSTATE is special because normal trap processing saves HPSTATE when + //it goes into a trap, and restores it when it returns. + return; + panic("Accessing Fullsystem register %d to %#x in SE mode\n", + miscReg, val); +#endif + } + setMiscRegNoEffect(miscReg, new_val); } void -ISA::setMiscRegNoEffect(int miscReg, const MiscReg val) +ISA::serialize(EventManager *em, std::ostream &os) { - miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val); + SERIALIZE_SCALAR(asi); + SERIALIZE_SCALAR(tick); + SERIALIZE_SCALAR(fprs); + SERIALIZE_SCALAR(gsr); + SERIALIZE_SCALAR(softint); + SERIALIZE_SCALAR(tick_cmpr); + SERIALIZE_SCALAR(stick); + SERIALIZE_SCALAR(stick_cmpr); + SERIALIZE_ARRAY(tpc,MaxTL); + SERIALIZE_ARRAY(tnpc,MaxTL); + SERIALIZE_ARRAY(tstate,MaxTL); + SERIALIZE_ARRAY(tt,MaxTL); + SERIALIZE_SCALAR(tba); + SERIALIZE_SCALAR(pstate); + SERIALIZE_SCALAR(tl); + SERIALIZE_SCALAR(pil); + SERIALIZE_SCALAR(cwp); + SERIALIZE_SCALAR(gl); + SERIALIZE_SCALAR(hpstate); + SERIALIZE_ARRAY(htstate,MaxTL); + SERIALIZE_SCALAR(hintp); + SERIALIZE_SCALAR(htba); + SERIALIZE_SCALAR(hstick_cmpr); + SERIALIZE_SCALAR(strandStatusReg); + SERIALIZE_SCALAR(fsr); + SERIALIZE_SCALAR(priContext); + SERIALIZE_SCALAR(secContext); + SERIALIZE_SCALAR(partId); + SERIALIZE_SCALAR(lsuCtrlReg); + SERIALIZE_ARRAY(scratchPad,8); + SERIALIZE_SCALAR(cpu_mondo_head); + SERIALIZE_SCALAR(cpu_mondo_tail); + SERIALIZE_SCALAR(dev_mondo_head); + SERIALIZE_SCALAR(dev_mondo_tail); + SERIALIZE_SCALAR(res_error_head); + SERIALIZE_SCALAR(res_error_tail); + SERIALIZE_SCALAR(nres_error_head); + SERIALIZE_SCALAR(nres_error_tail); +#if FULL_SYSTEM + Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; + ThreadContext *tc = NULL; + BaseCPU *cpu = NULL; + int tc_num = 0; + bool tick_intr_sched = true; + + if (tickCompare) + tc = tickCompare->getTC(); + else if (sTickCompare) + tc = sTickCompare->getTC(); + else if (hSTickCompare) + tc = hSTickCompare->getTC(); + else + tick_intr_sched = false; + + SERIALIZE_SCALAR(tick_intr_sched); + + if (tc) { + cpu = tc->getCpuPtr(); + tc_num = cpu->findContext(tc); + if (tickCompare && tickCompare->scheduled()) + tick_cmp = tickCompare->when(); + if (sTickCompare && sTickCompare->scheduled()) + stick_cmp = sTickCompare->when(); + if (hSTickCompare && hSTickCompare->scheduled()) + hstick_cmp = hSTickCompare->when(); + + SERIALIZE_OBJPTR(cpu); + SERIALIZE_SCALAR(tc_num); + SERIALIZE_SCALAR(tick_cmp); + SERIALIZE_SCALAR(stick_cmp); + SERIALIZE_SCALAR(hstick_cmp); + } +#endif } void -ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc) +ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) { - miscRegFile.setReg((MiscRegIndex)miscReg, val, tc); + UNSERIALIZE_SCALAR(asi); + UNSERIALIZE_SCALAR(tick); + UNSERIALIZE_SCALAR(fprs); + UNSERIALIZE_SCALAR(gsr); + UNSERIALIZE_SCALAR(softint); + UNSERIALIZE_SCALAR(tick_cmpr); + UNSERIALIZE_SCALAR(stick); + UNSERIALIZE_SCALAR(stick_cmpr); + UNSERIALIZE_ARRAY(tpc,MaxTL); + UNSERIALIZE_ARRAY(tnpc,MaxTL); + UNSERIALIZE_ARRAY(tstate,MaxTL); + UNSERIALIZE_ARRAY(tt,MaxTL); + UNSERIALIZE_SCALAR(tba); + UNSERIALIZE_SCALAR(pstate); + UNSERIALIZE_SCALAR(tl); + UNSERIALIZE_SCALAR(pil); + UNSERIALIZE_SCALAR(cwp); + UNSERIALIZE_SCALAR(gl); + UNSERIALIZE_SCALAR(hpstate); + UNSERIALIZE_ARRAY(htstate,MaxTL); + UNSERIALIZE_SCALAR(hintp); + UNSERIALIZE_SCALAR(htba); + UNSERIALIZE_SCALAR(hstick_cmpr); + UNSERIALIZE_SCALAR(strandStatusReg); + UNSERIALIZE_SCALAR(fsr); + UNSERIALIZE_SCALAR(priContext); + UNSERIALIZE_SCALAR(secContext); + UNSERIALIZE_SCALAR(partId); + UNSERIALIZE_SCALAR(lsuCtrlReg); + UNSERIALIZE_ARRAY(scratchPad,8); + UNSERIALIZE_SCALAR(cpu_mondo_head); + UNSERIALIZE_SCALAR(cpu_mondo_tail); + UNSERIALIZE_SCALAR(dev_mondo_head); + UNSERIALIZE_SCALAR(dev_mondo_tail); + UNSERIALIZE_SCALAR(res_error_head); + UNSERIALIZE_SCALAR(res_error_tail); + UNSERIALIZE_SCALAR(nres_error_head); + UNSERIALIZE_SCALAR(nres_error_tail); + +#if FULL_SYSTEM + Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; + ThreadContext *tc = NULL; + BaseCPU *cpu = NULL; + int tc_num; + bool tick_intr_sched; + UNSERIALIZE_SCALAR(tick_intr_sched); + if (tick_intr_sched) { + UNSERIALIZE_OBJPTR(cpu); + if (cpu) { + UNSERIALIZE_SCALAR(tc_num); + UNSERIALIZE_SCALAR(tick_cmp); + UNSERIALIZE_SCALAR(stick_cmp); + UNSERIALIZE_SCALAR(hstick_cmp); + tc = cpu->getContext(tc_num); + + if (tick_cmp) { + tickCompare = new TickCompareEvent(this, tc); + em->schedule(tickCompare, tick_cmp); + } + if (stick_cmp) { + sTickCompare = new STickCompareEvent(this, tc); + em->schedule(sTickCompare, stick_cmp); + } + if (hstick_cmp) { + hSTickCompare = new HSTickCompareEvent(this, tc); + em->schedule(hSTickCompare, hstick_cmp); + } + } + } + + #endif } int ISA::flattenIntIndex(int reg) { - int gl = miscRegFile.readRegNoEffect(MISCREG_GL); - int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP); + int gl = readMiscRegNoEffect(MISCREG_GL); + int cwp = readMiscRegNoEffect(MISCREG_CWP); //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); int newReg; //The total number of global registers @@ -132,16 +791,4 @@ ISA::flattenIntIndex(int reg) return newReg; } -void -ISA::serialize(EventManager *em, std::ostream &os) -{ - miscRegFile.serialize(em, os); -} - -void -ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) -{ - miscRegFile.unserialize(em, cp, section); -} - } diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index bba578ef1..c953be01b 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -31,22 +31,131 @@ #ifndef __ARCH_SPARC_ISA_HH__ #define __ARCH_SPARC_ISA_HH__ -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" +#include "config/full_system.hh" +#include "cpu/cpuevent.hh" + +#include +#include class Checkpoint; class EventManager; +class ThreadContext; namespace SparcISA { class ISA { - protected: - MiscRegFile miscRegFile; + private: + + /* ASR Registers */ + //uint64_t y; // Y (used in obsolete multiplication) + //uint8_t ccr; // Condition Code Register + uint8_t asi; // Address Space Identifier + uint64_t tick; // Hardware clock-tick counter + uint8_t fprs; // Floating-Point Register State + uint64_t gsr; // General Status Register + uint64_t softint; + uint64_t tick_cmpr; // Hardware tick compare registers + uint64_t stick; // Hardware clock-tick counter + uint64_t stick_cmpr; // Hardware tick compare registers + + + /* Privileged Registers */ + uint64_t tpc[MaxTL]; // Trap Program Counter (value from + // previous trap level) + uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from + // previous trap level) + uint64_t tstate[MaxTL]; // Trap State + uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured + // on the previous level) + uint64_t tba; // Trap Base Address + + uint16_t pstate; // Process State Register + uint8_t tl; // Trap Level + uint8_t pil; // Process Interrupt Register + uint8_t cwp; // Current Window Pointer + //uint8_t cansave; // Savable windows + //uint8_t canrestore; // Restorable windows + //uint8_t cleanwin; // Clean windows + //uint8_t otherwin; // Other windows + //uint8_t wstate; // Window State + uint8_t gl; // Global level register + + /** Hyperprivileged Registers */ + uint64_t hpstate; // Hyperprivileged State Register + uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register + uint64_t hintp; + uint64_t htba; // Hyperprivileged Trap Base Address register + uint64_t hstick_cmpr; // Hardware tick compare registers + + uint64_t strandStatusReg;// Per strand status register + + /** Floating point misc registers. */ + uint64_t fsr; // Floating-Point State Register + + /** MMU Internal Registers */ + uint16_t priContext; + uint16_t secContext; + uint16_t partId; + uint64_t lsuCtrlReg; + + uint64_t scratchPad[8]; + + uint64_t cpu_mondo_head; + uint64_t cpu_mondo_tail; + uint64_t dev_mondo_head; + uint64_t dev_mondo_tail; + uint64_t res_error_head; + uint64_t res_error_tail; + uint64_t nres_error_head; + uint64_t nres_error_tail; + + // These need to check the int_dis field and if 0 then + // set appropriate bit in softint and checkinterrutps on the cpu +#if FULL_SYSTEM + void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); + MiscReg readFSReg(int miscReg, ThreadContext * tc); + + // Update interrupt state on softint or pil change + void checkSoftInt(ThreadContext *tc); + + /** Process a tick compare event and generate an interrupt on the cpu if + * appropriate. */ + void processTickCompare(ThreadContext *tc); + void processSTickCompare(ThreadContext *tc); + void processHSTickCompare(ThreadContext *tc); + typedef CpuEventWrapper TickCompareEvent; + TickCompareEvent *tickCompare; + + typedef CpuEventWrapper STickCompareEvent; + STickCompareEvent *sTickCompare; + + typedef CpuEventWrapper HSTickCompareEvent; + HSTickCompareEvent *hSTickCompare; +#endif public: + void clear(); + void serialize(EventManager *em, std::ostream & os); + + void unserialize(EventManager *em, Checkpoint *cp, + const std::string & section); + + protected: + + bool isHyperPriv() { return (hpstate & (1 << 2)); } + bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } + bool isNonPriv() { return !isPriv(); } + + public: + MiscReg readMiscRegNoEffect(int miscReg); MiscReg readMiscReg(int miscReg, ThreadContext *tc); @@ -62,10 +171,6 @@ namespace SparcISA return reg; } - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); - ISA() { clear(); diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc deleted file mode 100644 index 38eba3862..000000000 --- a/src/arch/sparc/miscregfile.cc +++ /dev/null @@ -1,724 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/sparc/asi.hh" -#include "arch/sparc/miscregfile.hh" -#include "base/bitfield.hh" -#include "base/trace.hh" -#include "config/full_system.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" - -using namespace SparcISA; -using namespace std; - -class Checkpoint; - -enum RegMask -{ - PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12) -}; - -void MiscRegFile::clear() -{ - //y = 0; - //ccr = 0; - asi = 0; - tick = ULL(1) << 63; - fprs = 0; - gsr = 0; - softint = 0; - tick_cmpr = 0; - stick = 0; - stick_cmpr = 0; - memset(tpc, 0, sizeof(tpc)); - memset(tnpc, 0, sizeof(tnpc)); - memset(tstate, 0, sizeof(tstate)); - memset(tt, 0, sizeof(tt)); - pstate = 0; - tl = 0; - pil = 0; - cwp = 0; - //cansave = 0; - //canrestore = 0; - //cleanwin = 0; - //otherwin = 0; - //wstate = 0; - gl = 0; - //In a T1, bit 11 is apparently always 1 - hpstate = (1 << 11); - memset(htstate, 0, sizeof(htstate)); - hintp = 0; - htba = 0; - hstick_cmpr = 0; - //This is set this way in Legion for some reason - strandStatusReg = 0x50000; - fsr = 0; - - priContext = 0; - secContext = 0; - partId = 0; - lsuCtrlReg = 0; - - memset(scratchPad, 0, sizeof(scratchPad)); -#if FULL_SYSTEM - tickCompare = NULL; - sTickCompare = NULL; - hSTickCompare = NULL; -#endif -} - -MiscReg MiscRegFile::readRegNoEffect(int miscReg) -{ - - // The three miscRegs are moved up from the switch statement - // due to more frequent calls. - - if (miscReg == MISCREG_GL) - return gl; - if (miscReg == MISCREG_CWP) - return cwp; - if (miscReg == MISCREG_TLB_DATA) { - /* Package up all the data for the tlb: - * 6666555555555544444444443333333333222222222211111111110000000000 - * 3210987654321098765432109876543210987654321098765432109876543210 - * secContext | priContext | |tl|partid| |||||^hpriv - * ||||^red - * |||^priv - * ||^am - * |^lsuim - * ^lsudm - */ - return bits((uint64_t)hpstate,2,2) | - bits((uint64_t)hpstate,5,5) << 1 | - bits((uint64_t)pstate,3,2) << 2 | - bits((uint64_t)lsuCtrlReg,3,2) << 4 | - bits((uint64_t)partId,7,0) << 8 | - bits((uint64_t)tl,2,0) << 16 | - (uint64_t)priContext << 32 | - (uint64_t)secContext << 48; - } - - switch (miscReg) { - //case MISCREG_TLB_DATA: - // [original contents see above] - //case MISCREG_Y: - // return y; - //case MISCREG_CCR: - // return ccr; - case MISCREG_ASI: - return asi; - case MISCREG_FPRS: - return fprs; - case MISCREG_TICK: - return tick; - case MISCREG_PCR: - panic("PCR not implemented\n"); - case MISCREG_PIC: - panic("PIC not implemented\n"); - case MISCREG_GSR: - return gsr; - case MISCREG_SOFTINT: - return softint; - case MISCREG_TICK_CMPR: - return tick_cmpr; - case MISCREG_STICK: - return stick; - case MISCREG_STICK_CMPR: - return stick_cmpr; - - /** Privilged Registers */ - case MISCREG_TPC: - return tpc[tl-1]; - case MISCREG_TNPC: - return tnpc[tl-1]; - case MISCREG_TSTATE: - return tstate[tl-1]; - case MISCREG_TT: - return tt[tl-1]; - case MISCREG_PRIVTICK: - panic("Priviliged access to tick registers not implemented\n"); - case MISCREG_TBA: - return tba; - case MISCREG_PSTATE: - return pstate; - case MISCREG_TL: - return tl; - case MISCREG_PIL: - return pil; - //CWP, GL moved - //case MISCREG_CWP: - // return cwp; - //case MISCREG_CANSAVE: - // return cansave; - //case MISCREG_CANRESTORE: - // return canrestore; - //case MISCREG_CLEANWIN: - // return cleanwin; - //case MISCREG_OTHERWIN: - // return otherwin; - //case MISCREG_WSTATE: - // return wstate; - //case MISCREG_GL: - // return gl; - - /** Hyper privileged registers */ - case MISCREG_HPSTATE: - return hpstate; - case MISCREG_HTSTATE: - return htstate[tl-1]; - case MISCREG_HINTP: - return hintp; - case MISCREG_HTBA: - return htba; - case MISCREG_STRAND_STS_REG: - return strandStatusReg; - case MISCREG_HSTICK_CMPR: - return hstick_cmpr; - - /** Floating Point Status Register */ - case MISCREG_FSR: - DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr); - return fsr; - - case MISCREG_MMU_P_CONTEXT: - return priContext; - case MISCREG_MMU_S_CONTEXT: - return secContext; - case MISCREG_MMU_PART_ID: - return partId; - case MISCREG_MMU_LSU_CTRL: - return lsuCtrlReg; - - case MISCREG_SCRATCHPAD_R0: - return scratchPad[0]; - case MISCREG_SCRATCHPAD_R1: - return scratchPad[1]; - case MISCREG_SCRATCHPAD_R2: - return scratchPad[2]; - case MISCREG_SCRATCHPAD_R3: - return scratchPad[3]; - case MISCREG_SCRATCHPAD_R4: - return scratchPad[4]; - case MISCREG_SCRATCHPAD_R5: - return scratchPad[5]; - case MISCREG_SCRATCHPAD_R6: - return scratchPad[6]; - case MISCREG_SCRATCHPAD_R7: - return scratchPad[7]; - case MISCREG_QUEUE_CPU_MONDO_HEAD: - return cpu_mondo_head; - case MISCREG_QUEUE_CPU_MONDO_TAIL: - return cpu_mondo_tail; - case MISCREG_QUEUE_DEV_MONDO_HEAD: - return dev_mondo_head; - case MISCREG_QUEUE_DEV_MONDO_TAIL: - return dev_mondo_tail; - case MISCREG_QUEUE_RES_ERROR_HEAD: - return res_error_head; - case MISCREG_QUEUE_RES_ERROR_TAIL: - return res_error_tail; - case MISCREG_QUEUE_NRES_ERROR_HEAD: - return nres_error_head; - case MISCREG_QUEUE_NRES_ERROR_TAIL: - return nres_error_tail; - default: - panic("Miscellaneous register %d not implemented\n", miscReg); - } -} - -MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) -{ - switch (miscReg) { - // tick and stick are aliased to each other in niagra - // well store the tick data in stick and the interrupt bit in tick - case MISCREG_STICK: - case MISCREG_TICK: - case MISCREG_PRIVTICK: - // I'm not sure why legion ignores the lowest two bits, but we'll go - // with it - // change from curCycle() to instCount() until we're done with legion - DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n", - tc->getCpuPtr()->instCount(), stick); - return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | - mbits(tick,63,63); - case MISCREG_FPRS: - // in legion if fp is enabled du and dl are set - return fprs | 0x3; - case MISCREG_PCR: - case MISCREG_PIC: - panic("Performance Instrumentation not impl\n"); - case MISCREG_SOFTINT_CLR: - case MISCREG_SOFTINT_SET: - panic("Can read from softint clr/set\n"); - case MISCREG_SOFTINT: - case MISCREG_TICK_CMPR: - case MISCREG_STICK_CMPR: - case MISCREG_HINTP: - case MISCREG_HTSTATE: - case MISCREG_HTBA: - case MISCREG_HVER: - case MISCREG_STRAND_STS_REG: - case MISCREG_HSTICK_CMPR: - case MISCREG_QUEUE_CPU_MONDO_HEAD: - case MISCREG_QUEUE_CPU_MONDO_TAIL: - case MISCREG_QUEUE_DEV_MONDO_HEAD: - case MISCREG_QUEUE_DEV_MONDO_TAIL: - case MISCREG_QUEUE_RES_ERROR_HEAD: - case MISCREG_QUEUE_RES_ERROR_TAIL: - case MISCREG_QUEUE_NRES_ERROR_HEAD: - case MISCREG_QUEUE_NRES_ERROR_TAIL: -#if FULL_SYSTEM - case MISCREG_HPSTATE: - return readFSReg(miscReg, tc); -#else - case MISCREG_HPSTATE: - //HPSTATE is special because because sometimes in privilege - //checks for instructions it will read HPSTATE to make sure - //the priv. level is ok So, we'll just have to tell it it - //isn't, instead of panicing. - return 0; - - panic("Accessing Fullsystem register %d in SE mode\n", miscReg); -#endif - - } - return readRegNoEffect(miscReg); -} - -void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) -{ - switch (miscReg) { -// case MISCREG_Y: -// y = val; -// break; -// case MISCREG_CCR: -// ccr = val; -// break; - case MISCREG_ASI: - asi = val; - break; - case MISCREG_FPRS: - fprs = val; - break; - case MISCREG_TICK: - tick = val; - break; - case MISCREG_PCR: - panic("PCR not implemented\n"); - case MISCREG_PIC: - panic("PIC not implemented\n"); - case MISCREG_GSR: - gsr = val; - break; - case MISCREG_SOFTINT: - softint = val; - break; - case MISCREG_TICK_CMPR: - tick_cmpr = val; - break; - case MISCREG_STICK: - stick = val; - break; - case MISCREG_STICK_CMPR: - stick_cmpr = val; - break; - - /** Privilged Registers */ - case MISCREG_TPC: - tpc[tl-1] = val; - break; - case MISCREG_TNPC: - tnpc[tl-1] = val; - break; - case MISCREG_TSTATE: - tstate[tl-1] = val; - break; - case MISCREG_TT: - tt[tl-1] = val; - break; - case MISCREG_PRIVTICK: - panic("Priviliged access to tick regesiters not implemented\n"); - case MISCREG_TBA: - // clear lower 7 bits on writes. - tba = val & ULL(~0x7FFF); - break; - case MISCREG_PSTATE: - pstate = (val & PSTATE_MASK); - break; - case MISCREG_TL: - tl = val; - break; - case MISCREG_PIL: - pil = val; - break; - case MISCREG_CWP: - cwp = val; - break; -// case MISCREG_CANSAVE: -// cansave = val; -// break; -// case MISCREG_CANRESTORE: -// canrestore = val; -// break; -// case MISCREG_CLEANWIN: -// cleanwin = val; -// break; -// case MISCREG_OTHERWIN: -// otherwin = val; -// break; -// case MISCREG_WSTATE: -// wstate = val; -// break; - case MISCREG_GL: - gl = val; - break; - - /** Hyper privileged registers */ - case MISCREG_HPSTATE: - hpstate = val; - break; - case MISCREG_HTSTATE: - htstate[tl-1] = val; - break; - case MISCREG_HINTP: - hintp = val; - case MISCREG_HTBA: - htba = val; - break; - case MISCREG_STRAND_STS_REG: - strandStatusReg = val; - break; - case MISCREG_HSTICK_CMPR: - hstick_cmpr = val; - break; - - /** Floating Point Status Register */ - case MISCREG_FSR: - fsr = val; - DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr); - break; - - case MISCREG_MMU_P_CONTEXT: - priContext = val; - break; - case MISCREG_MMU_S_CONTEXT: - secContext = val; - break; - case MISCREG_MMU_PART_ID: - partId = val; - break; - case MISCREG_MMU_LSU_CTRL: - lsuCtrlReg = val; - break; - - case MISCREG_SCRATCHPAD_R0: - scratchPad[0] = val; - break; - case MISCREG_SCRATCHPAD_R1: - scratchPad[1] = val; - break; - case MISCREG_SCRATCHPAD_R2: - scratchPad[2] = val; - break; - case MISCREG_SCRATCHPAD_R3: - scratchPad[3] = val; - break; - case MISCREG_SCRATCHPAD_R4: - scratchPad[4] = val; - break; - case MISCREG_SCRATCHPAD_R5: - scratchPad[5] = val; - break; - case MISCREG_SCRATCHPAD_R6: - scratchPad[6] = val; - break; - case MISCREG_SCRATCHPAD_R7: - scratchPad[7] = val; - break; - case MISCREG_QUEUE_CPU_MONDO_HEAD: - cpu_mondo_head = val; - break; - case MISCREG_QUEUE_CPU_MONDO_TAIL: - cpu_mondo_tail = val; - break; - case MISCREG_QUEUE_DEV_MONDO_HEAD: - dev_mondo_head = val; - break; - case MISCREG_QUEUE_DEV_MONDO_TAIL: - dev_mondo_tail = val; - break; - case MISCREG_QUEUE_RES_ERROR_HEAD: - res_error_head = val; - break; - case MISCREG_QUEUE_RES_ERROR_TAIL: - res_error_tail = val; - break; - case MISCREG_QUEUE_NRES_ERROR_HEAD: - nres_error_head = val; - break; - case MISCREG_QUEUE_NRES_ERROR_TAIL: - nres_error_tail = val; - break; - default: - panic("Miscellaneous register %d not implemented\n", miscReg); - } -} - -void MiscRegFile::setReg(int miscReg, - const MiscReg &val, ThreadContext * tc) -{ - MiscReg new_val = val; - - switch (miscReg) { - case MISCREG_STICK: - case MISCREG_TICK: - // stick and tick are same thing on niagra - // use stick for offset and tick for holding intrrupt bit - stick = mbits(val,62,0) - tc->getCpuPtr()->instCount(); - tick = mbits(val,63,63); - DPRINTF(Timer, "Writing TICK=%#X\n", val); - break; - case MISCREG_FPRS: - //Configure the fpu based on the fprs - break; - case MISCREG_PCR: - //Set up performance counting based on pcr value - break; - case MISCREG_PSTATE: - pstate = val & PSTATE_MASK; - return; - case MISCREG_TL: - tl = val; -#if FULL_SYSTEM - if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) - tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); - else - tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); -#endif - return; - case MISCREG_CWP: - new_val = val >= NWindows ? NWindows - 1 : val; - if (val >= NWindows) - new_val = NWindows - 1; - break; - case MISCREG_GL: - break; - case MISCREG_PIL: - case MISCREG_SOFTINT: - case MISCREG_SOFTINT_SET: - case MISCREG_SOFTINT_CLR: - case MISCREG_TICK_CMPR: - case MISCREG_STICK_CMPR: - case MISCREG_HINTP: - case MISCREG_HTSTATE: - case MISCREG_HTBA: - case MISCREG_HVER: - case MISCREG_STRAND_STS_REG: - case MISCREG_HSTICK_CMPR: - case MISCREG_QUEUE_CPU_MONDO_HEAD: - case MISCREG_QUEUE_CPU_MONDO_TAIL: - case MISCREG_QUEUE_DEV_MONDO_HEAD: - case MISCREG_QUEUE_DEV_MONDO_TAIL: - case MISCREG_QUEUE_RES_ERROR_HEAD: - case MISCREG_QUEUE_RES_ERROR_TAIL: - case MISCREG_QUEUE_NRES_ERROR_HEAD: - case MISCREG_QUEUE_NRES_ERROR_TAIL: -#if FULL_SYSTEM - case MISCREG_HPSTATE: - setFSReg(miscReg, val, tc); - return; -#else - case MISCREG_HPSTATE: - //HPSTATE is special because normal trap processing saves HPSTATE when - //it goes into a trap, and restores it when it returns. - return; - panic("Accessing Fullsystem register %d to %#x in SE mode\n", - miscReg, val); -#endif - } - setRegNoEffect(miscReg, new_val); -} - -void -MiscRegFile::serialize(EventManager *em, std::ostream &os) -{ - SERIALIZE_SCALAR(asi); - SERIALIZE_SCALAR(tick); - SERIALIZE_SCALAR(fprs); - SERIALIZE_SCALAR(gsr); - SERIALIZE_SCALAR(softint); - SERIALIZE_SCALAR(tick_cmpr); - SERIALIZE_SCALAR(stick); - SERIALIZE_SCALAR(stick_cmpr); - SERIALIZE_ARRAY(tpc,MaxTL); - SERIALIZE_ARRAY(tnpc,MaxTL); - SERIALIZE_ARRAY(tstate,MaxTL); - SERIALIZE_ARRAY(tt,MaxTL); - SERIALIZE_SCALAR(tba); - SERIALIZE_SCALAR(pstate); - SERIALIZE_SCALAR(tl); - SERIALIZE_SCALAR(pil); - SERIALIZE_SCALAR(cwp); - SERIALIZE_SCALAR(gl); - SERIALIZE_SCALAR(hpstate); - SERIALIZE_ARRAY(htstate,MaxTL); - SERIALIZE_SCALAR(hintp); - SERIALIZE_SCALAR(htba); - SERIALIZE_SCALAR(hstick_cmpr); - SERIALIZE_SCALAR(strandStatusReg); - SERIALIZE_SCALAR(fsr); - SERIALIZE_SCALAR(priContext); - SERIALIZE_SCALAR(secContext); - SERIALIZE_SCALAR(partId); - SERIALIZE_SCALAR(lsuCtrlReg); - SERIALIZE_ARRAY(scratchPad,8); - SERIALIZE_SCALAR(cpu_mondo_head); - SERIALIZE_SCALAR(cpu_mondo_tail); - SERIALIZE_SCALAR(dev_mondo_head); - SERIALIZE_SCALAR(dev_mondo_tail); - SERIALIZE_SCALAR(res_error_head); - SERIALIZE_SCALAR(res_error_tail); - SERIALIZE_SCALAR(nres_error_head); - SERIALIZE_SCALAR(nres_error_tail); -#if FULL_SYSTEM - Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; - ThreadContext *tc = NULL; - BaseCPU *cpu = NULL; - int tc_num = 0; - bool tick_intr_sched = true; - - if (tickCompare) - tc = tickCompare->getTC(); - else if (sTickCompare) - tc = sTickCompare->getTC(); - else if (hSTickCompare) - tc = hSTickCompare->getTC(); - else - tick_intr_sched = false; - - SERIALIZE_SCALAR(tick_intr_sched); - - if (tc) { - cpu = tc->getCpuPtr(); - tc_num = cpu->findContext(tc); - if (tickCompare && tickCompare->scheduled()) - tick_cmp = tickCompare->when(); - if (sTickCompare && sTickCompare->scheduled()) - stick_cmp = sTickCompare->when(); - if (hSTickCompare && hSTickCompare->scheduled()) - hstick_cmp = hSTickCompare->when(); - - SERIALIZE_OBJPTR(cpu); - SERIALIZE_SCALAR(tc_num); - SERIALIZE_SCALAR(tick_cmp); - SERIALIZE_SCALAR(stick_cmp); - SERIALIZE_SCALAR(hstick_cmp); - } -#endif -} - -void -MiscRegFile::unserialize(EventManager *em, Checkpoint *cp, - const string §ion) -{ - UNSERIALIZE_SCALAR(asi); - UNSERIALIZE_SCALAR(tick); - UNSERIALIZE_SCALAR(fprs); - UNSERIALIZE_SCALAR(gsr); - UNSERIALIZE_SCALAR(softint); - UNSERIALIZE_SCALAR(tick_cmpr); - UNSERIALIZE_SCALAR(stick); - UNSERIALIZE_SCALAR(stick_cmpr); - UNSERIALIZE_ARRAY(tpc,MaxTL); - UNSERIALIZE_ARRAY(tnpc,MaxTL); - UNSERIALIZE_ARRAY(tstate,MaxTL); - UNSERIALIZE_ARRAY(tt,MaxTL); - UNSERIALIZE_SCALAR(tba); - UNSERIALIZE_SCALAR(pstate); - UNSERIALIZE_SCALAR(tl); - UNSERIALIZE_SCALAR(pil); - UNSERIALIZE_SCALAR(cwp); - UNSERIALIZE_SCALAR(gl); - UNSERIALIZE_SCALAR(hpstate); - UNSERIALIZE_ARRAY(htstate,MaxTL); - UNSERIALIZE_SCALAR(hintp); - UNSERIALIZE_SCALAR(htba); - UNSERIALIZE_SCALAR(hstick_cmpr); - UNSERIALIZE_SCALAR(strandStatusReg); - UNSERIALIZE_SCALAR(fsr); - UNSERIALIZE_SCALAR(priContext); - UNSERIALIZE_SCALAR(secContext); - UNSERIALIZE_SCALAR(partId); - UNSERIALIZE_SCALAR(lsuCtrlReg); - UNSERIALIZE_ARRAY(scratchPad,8); - UNSERIALIZE_SCALAR(cpu_mondo_head); - UNSERIALIZE_SCALAR(cpu_mondo_tail); - UNSERIALIZE_SCALAR(dev_mondo_head); - UNSERIALIZE_SCALAR(dev_mondo_tail); - UNSERIALIZE_SCALAR(res_error_head); - UNSERIALIZE_SCALAR(res_error_tail); - UNSERIALIZE_SCALAR(nres_error_head); - UNSERIALIZE_SCALAR(nres_error_tail); - -#if FULL_SYSTEM - Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; - ThreadContext *tc = NULL; - BaseCPU *cpu = NULL; - int tc_num; - bool tick_intr_sched; - UNSERIALIZE_SCALAR(tick_intr_sched); - if (tick_intr_sched) { - UNSERIALIZE_OBJPTR(cpu); - if (cpu) { - UNSERIALIZE_SCALAR(tc_num); - UNSERIALIZE_SCALAR(tick_cmp); - UNSERIALIZE_SCALAR(stick_cmp); - UNSERIALIZE_SCALAR(hstick_cmp); - tc = cpu->getContext(tc_num); - - if (tick_cmp) { - tickCompare = new TickCompareEvent(this, tc); - em->schedule(tickCompare, tick_cmp); - } - if (stick_cmp) { - sTickCompare = new STickCompareEvent(this, tc); - em->schedule(sTickCompare, stick_cmp); - } - if (hstick_cmp) { - hSTickCompare = new HSTickCompareEvent(this, tc); - em->schedule(hSTickCompare, hstick_cmp); - } - } - } - - #endif -} diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh deleted file mode 100644 index 36c309db2..000000000 --- a/src/arch/sparc/miscregfile.hh +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_SPARC_MISCREGFILE_HH__ -#define __ARCH_SPARC_MISCREGFILE_HH__ - -#include "arch/sparc/faults.hh" -#include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregs.hh" -#include "arch/sparc/registers.hh" -#include "arch/sparc/types.hh" -#include "cpu/cpuevent.hh" - -#include - -class Checkpoint; - -namespace SparcISA -{ - // The control registers, broken out into fields - class MiscRegFile - { - private: - - /* ASR Registers */ - //uint64_t y; // Y (used in obsolete multiplication) - //uint8_t ccr; // Condition Code Register - uint8_t asi; // Address Space Identifier - uint64_t tick; // Hardware clock-tick counter - uint8_t fprs; // Floating-Point Register State - uint64_t gsr; // General Status Register - uint64_t softint; - uint64_t tick_cmpr; // Hardware tick compare registers - uint64_t stick; // Hardware clock-tick counter - uint64_t stick_cmpr; // Hardware tick compare registers - - - /* Privileged Registers */ - uint64_t tpc[MaxTL]; // Trap Program Counter (value from - // previous trap level) - uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from - // previous trap level) - uint64_t tstate[MaxTL]; // Trap State - uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured - // on the previous level) - uint64_t tba; // Trap Base Address - - uint16_t pstate; // Process State Register - uint8_t tl; // Trap Level - uint8_t pil; // Process Interrupt Register - uint8_t cwp; // Current Window Pointer - //uint8_t cansave; // Savable windows - //uint8_t canrestore; // Restorable windows - //uint8_t cleanwin; // Clean windows - //uint8_t otherwin; // Other windows - //uint8_t wstate; // Window State - uint8_t gl; // Global level register - - /** Hyperprivileged Registers */ - uint64_t hpstate; // Hyperprivileged State Register - uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register - uint64_t hintp; - uint64_t htba; // Hyperprivileged Trap Base Address register - uint64_t hstick_cmpr; // Hardware tick compare registers - - uint64_t strandStatusReg;// Per strand status register - - /** Floating point misc registers. */ - uint64_t fsr; // Floating-Point State Register - - /** MMU Internal Registers */ - uint16_t priContext; - uint16_t secContext; - uint16_t partId; - uint64_t lsuCtrlReg; - - uint64_t scratchPad[8]; - - uint64_t cpu_mondo_head; - uint64_t cpu_mondo_tail; - uint64_t dev_mondo_head; - uint64_t dev_mondo_tail; - uint64_t res_error_head; - uint64_t res_error_tail; - uint64_t nres_error_head; - uint64_t nres_error_tail; - - // These need to check the int_dis field and if 0 then - // set appropriate bit in softint and checkinterrutps on the cpu -#if FULL_SYSTEM - void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); - MiscReg readFSReg(int miscReg, ThreadContext * tc); - - // Update interrupt state on softint or pil change - void checkSoftInt(ThreadContext *tc); - - /** Process a tick compare event and generate an interrupt on the cpu if - * appropriate. */ - void processTickCompare(ThreadContext *tc); - void processSTickCompare(ThreadContext *tc); - void processHSTickCompare(ThreadContext *tc); - - typedef CpuEventWrapper TickCompareEvent; - TickCompareEvent *tickCompare; - - typedef CpuEventWrapper STickCompareEvent; - STickCompareEvent *sTickCompare; - - typedef CpuEventWrapper HSTickCompareEvent; - HSTickCompareEvent *hSTickCompare; -#endif - public: - - void clear(); - - MiscRegFile() - { - clear(); - } - - MiscReg readRegNoEffect(int miscReg); - - MiscReg readReg(int miscReg, ThreadContext *tc); - - void setRegNoEffect(int miscReg, const MiscReg &val); - - void setReg(int miscReg, - const MiscReg &val, ThreadContext * tc); - - void serialize(EventManager *em, std::ostream & os); - - void unserialize(EventManager *em, Checkpoint *cp, - const std::string & section); - - void copyMiscRegs(ThreadContext * tc); - - protected: - - bool isHyperPriv() { return (hpstate & (1 << 2)); } - bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } - bool isNonPriv() { return !isPriv(); } - }; -} - -#endif diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 8c2ab1efd..c4ab4fe79 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -31,7 +31,7 @@ #ifndef __ARCH_SPARC_PREDECODER_HH__ #define __ARCH_SPARC_PREDECODER_HH__ -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" #include "base/bitfield.hh" #include "base/misc.hh" diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index b35190d1b..2ec483bab 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -32,7 +32,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/handlers.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/process.hh" #include "arch/sparc/types.hh" #include "base/loader/object_file.hh" diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 64d73c3c1..1b84a0784 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -31,7 +31,7 @@ #include #include "arch/sparc/asi.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/tlb.hh" #include "base/bitfield.hh" #include "base/trace.hh" diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index d126d5944..95381db38 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -26,8 +26,9 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "arch/sparc/isa.hh" #include "arch/sparc/kernel_stats.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" @@ -39,7 +40,7 @@ using namespace std; void -MiscRegFile::checkSoftInt(ThreadContext *tc) +ISA::checkSoftInt(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -84,7 +85,7 @@ getMiscRegName(RegIndex index) } void -MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) +ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -92,18 +93,18 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) switch (miscReg) { /* Full system only ASRs */ case MISCREG_SOFTINT: - setRegNoEffect(miscReg, val);; + setMiscRegNoEffect(miscReg, val);; checkSoftInt(tc); break; case MISCREG_SOFTINT_CLR: - return setReg(MISCREG_SOFTINT, ~val & softint, tc); + return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); case MISCREG_SOFTINT_SET: - return setReg(MISCREG_SOFTINT, val | softint, tc); + return setMiscReg(MISCREG_SOFTINT, val | softint, tc); case MISCREG_TICK_CMPR: if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) cpu->deschedule(tickCompare); time = (tick_cmpr & mask(63)) - (tick & mask(63)); @@ -118,7 +119,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) cpu->deschedule(sTickCompare); time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - @@ -132,10 +133,10 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_PSTATE: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); case MISCREG_PIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); checkSoftInt(tc); break; @@ -143,7 +144,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) panic("Shouldn't be writing HVER\n"); case MISCREG_HINTP: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (hintp) cpu->postInterrupt(IT_HINTP, 0); else @@ -152,12 +153,12 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_HTBA: // clear lower 7 bits on writes. - setRegNoEffect(miscReg, val & ULL(~0x7FFF)); + setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); break; case MISCREG_QUEUE_CPU_MONDO_HEAD: case MISCREG_QUEUE_CPU_MONDO_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (cpu_mondo_head != cpu_mondo_tail) cpu->postInterrupt(IT_CPU_MONDO, 0); else @@ -165,7 +166,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_DEV_MONDO_HEAD: case MISCREG_QUEUE_DEV_MONDO_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (dev_mondo_head != dev_mondo_tail) cpu->postInterrupt(IT_DEV_MONDO, 0); else @@ -173,7 +174,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_RES_ERROR_HEAD: case MISCREG_QUEUE_RES_ERROR_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if (res_error_head != res_error_tail) cpu->postInterrupt(IT_RES_ERROR, 0); else @@ -181,14 +182,14 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) break; case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); // This one doesn't have an interrupt to report to the guest OS break; case MISCREG_HSTICK_CMPR: if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) cpu->deschedule(hSTickCompare); time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - @@ -203,7 +204,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_HPSTATE: // T1000 spec says impl. dependent val must always be 1 - setRegNoEffect(miscReg, val | HPSTATE::id); + setMiscRegNoEffect(miscReg, val | HPSTATE::id); #if FULL_SYSTEM if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); @@ -212,13 +213,13 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) #endif break; case MISCREG_HTSTATE: - setRegNoEffect(miscReg, val); + setMiscRegNoEffect(miscReg, val); break; case MISCREG_STRAND_STS_REG: if (bits(val,2,2)) panic("No support for setting spec_en bit\n"); - setRegNoEffect(miscReg, bits(val,0,0)); + setMiscRegNoEffect(miscReg, bits(val,0,0)); if (!bits(val,0,0)) { DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep @@ -235,7 +236,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) } MiscReg -MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) +ISA::readFSReg(int miscReg, ThreadContext * tc) { uint64_t temp; @@ -257,10 +258,10 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) case MISCREG_HINTP: case MISCREG_HTSTATE: case MISCREG_HSTICK_CMPR: - return readRegNoEffect(miscReg) ; + return readMiscRegNoEffect(miscReg) ; case MISCREG_HTBA: - return readRegNoEffect(miscReg) & ULL(~0x7FFF); + return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: // XXX set to match Legion return ULL(0x3e) << 48 | @@ -275,7 +276,7 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) int x; sys = tc->getSystemPtr(); - temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative); + temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); // Check that the CPU array is fully populated // (by calling getNumCPus()) assert(sys->numContexts() > tc->contextId()); @@ -309,13 +310,13 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) } void -MiscRegFile::processTickCompare(ThreadContext *tc) +ISA::processTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } void -MiscRegFile::processSTickCompare(ThreadContext *tc) +ISA::processSTickCompare(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -331,14 +332,14 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { - setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); + setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } } else cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); } void -MiscRegFile::processHSTickCompare(ThreadContext *tc) +ISA::processHSTickCompare(ThreadContext *tc) { BaseCPU *cpu = tc->getCpuPtr(); @@ -357,7 +358,7 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { - setReg(MISCREG_HINTP, 1, tc); + setMiscReg(MISCREG_HINTP, 1, tc); } // Need to do something to cause interrupt to happen here !!! @todo } else diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 551570723..2b9059371 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -33,7 +33,7 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregfile.hh" +#include "arch/sparc/registers.hh" #include "arch/sparc/tlb.hh" #include "base/misc.hh" #include "base/bitfield.hh" -- cgit v1.2.3 From 64fe7af51a4cfd01886bf524f4f37d7e1a31fa9f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Jul 2009 01:01:47 -0700 Subject: SPARC: Set up a lookup table for integer register flattening. Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s --- src/arch/sparc/isa.cc | 116 ++++++++++++++++++---------------------------- src/arch/sparc/isa.hh | 34 +++++++++++++- src/arch/sparc/process.cc | 2 +- src/arch/sparc/utility.cc | 16 +++---- 4 files changed, 88 insertions(+), 80 deletions(-) (limited to 'src/arch/sparc') diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 61366937f..3226b4e42 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -44,9 +44,47 @@ enum RegMask PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12) }; +void +ISA::reloadRegMap() +{ + installGlobals(gl, CurrentGlobalsOffset); + installWindow(cwp, CurrentWindowOffset); + // Microcode registers. + for (int i = 0; i < NumMicroIntRegs; i++) + intRegMap[MicroIntOffset + i] = i + TotalGlobals + NWindows * 16; + installGlobals(gl, NextGlobalsOffset); + installWindow(cwp - 1, NextWindowOffset); + installGlobals(gl, PreviousGlobalsOffset); + installWindow(cwp + 1, PreviousWindowOffset); +} + +void +ISA::installWindow(int cwp, int offset) +{ + assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs); + RegIndex *mapChunk = intRegMap + offset; + for (int i = 0; i < NumWindowedRegs; i++) + mapChunk[i] = TotalGlobals + + ((i - cwp * RegsPerWindow + TotalWindowed) % (TotalWindowed)); +} + +void +ISA::installGlobals(int gl, int offset) +{ + assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs); + RegIndex *mapChunk = intRegMap + offset; + mapChunk[0] = 0; + for (int i = 1; i < NumGlobalRegs; i++) + mapChunk[i] = i + gl * NumGlobalRegs; +} + void ISA::clear() { + cwp = 0; + gl = 0; + reloadRegMap(); + //y = 0; //ccr = 0; asi = 0; @@ -64,13 +102,11 @@ ISA::clear() pstate = 0; tl = 0; pil = 0; - cwp = 0; //cansave = 0; //canrestore = 0; //cleanwin = 0; //otherwin = 0; //wstate = 0; - gl = 0; //In a T1, bit 11 is apparently always 1 hpstate = (1 << 11); memset(htstate, 0, sizeof(htstate)); @@ -530,8 +566,15 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) new_val = val >= NWindows ? NWindows - 1 : val; if (val >= NWindows) new_val = NWindows - 1; + + installWindow(new_val, CurrentWindowOffset); + installWindow(new_val - 1, NextWindowOffset); + installWindow(new_val + 1, PreviousWindowOffset); break; case MISCREG_GL: + installGlobals(val, CurrentGlobalsOffset); + installGlobals(val, NextGlobalsOffset); + installGlobals(val, PreviousGlobalsOffset); break; case MISCREG_PIL: case MISCREG_SOFTINT: @@ -668,6 +711,7 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(pil); UNSERIALIZE_SCALAR(cwp); UNSERIALIZE_SCALAR(gl); + reloadRegMap(); UNSERIALIZE_SCALAR(hpstate); UNSERIALIZE_ARRAY(htstate,MaxTL); UNSERIALIZE_SCALAR(hintp); @@ -723,72 +767,4 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) #endif } -int -ISA::flattenIntIndex(int reg) -{ - int gl = readMiscRegNoEffect(MISCREG_GL); - int cwp = readMiscRegNoEffect(MISCREG_CWP); - //DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); - int newReg; - //The total number of global registers - int numGlobals = (MaxGL + 1) * 8; - if(reg < 8) - { - //Global register - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else if(reg < NumIntArchRegs) - { - //Regular windowed register - //Put it in the window pointed to by cwp - newReg = numGlobals + - ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16)); - } - else if(reg < NumIntArchRegs + NumMicroIntRegs) - { - //Microcode register - //Displace from the end of the regular registers - newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16; - } - else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the next window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the previous window - //Put it in the window before the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs) - { - reg -= (2 * NumIntArchRegs + NumMicroIntRegs); - if(reg < 8) - { - //Global register from the previous window - //Put it in the appropriate set of globals - newReg = reg + gl * 8; - } - else - { - //Windowed register from the next window - //Put it in the window after the one pointed to by cwp - newReg = numGlobals + - ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16)); - } - } - else - panic("Tried to flatten invalid register index %d!\n", reg); - DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg); - return newReg; -} - } diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index c953be01b..9b4fd50d0 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -139,6 +139,31 @@ namespace SparcISA &ISA::processHSTickCompare> HSTickCompareEvent; HSTickCompareEvent *hSTickCompare; #endif + + static const int NumGlobalRegs = 8; + static const int NumWindowedRegs = 24; + static const int WindowOverlap = 8; + + static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs; + static const int RegsPerWindow = NumWindowedRegs - WindowOverlap; + static const int TotalWindowed = NWindows * RegsPerWindow; + + enum InstIntRegOffsets { + CurrentGlobalsOffset = 0, + CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs, + MicroIntOffset = CurrentWindowOffset + NumWindowedRegs, + NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs, + NextWindowOffset = NextGlobalsOffset + NumGlobalRegs, + PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs, + PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs, + TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs + }; + + RegIndex intRegMap[TotalInstIntRegs]; + void installWindow(int cwp, int offset); + void installGlobals(int gl, int offset); + void reloadRegMap(); + public: void clear(); @@ -163,7 +188,14 @@ namespace SparcISA void setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc); - int flattenIntIndex(int reg); + int + flattenIntIndex(int reg) + { + assert(reg < TotalInstIntRegs); + RegIndex flatIndex = intRegMap[reg]; + assert(flatIndex < NumIntRegs); + return flatIndex; + } int flattenFloatIndex(int reg) diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 2ec483bab..89e853573 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -140,7 +140,7 @@ SparcLiveProcess::startup() //tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); tc->setIntReg(NumIntArchRegs + 5, NWindows); //Start with register window 0 - tc->setMiscRegNoEffect(MISCREG_CWP, 0); + tc->setMiscReg(MISCREG_CWP, 0); //Always use spill and fill traps 0 //tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); tc->setIntReg(NumIntArchRegs + 7, 0); diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index 9c9b833fe..84e700f6d 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -101,13 +101,13 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest) dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); - dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); + dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); // dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); // dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); // dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); // dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); // dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); - dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); + dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); // Hyperprivilged registers dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); @@ -180,16 +180,16 @@ copyRegs(ThreadContext *src, ThreadContext *dest) int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); //Globals for (int x = 0; x < MaxGL; ++x) { - src->setMiscRegNoEffect(MISCREG_GL, x); - dest->setMiscRegNoEffect(MISCREG_GL, x); + src->setMiscReg(MISCREG_GL, x); + dest->setMiscReg(MISCREG_GL, x); // Skip %g0 which is always zero. for (int y = 1; y < 8; y++) dest->setIntReg(y, src->readIntReg(y)); } //Locals and ins. Outs are all also ins. for (int x = 0; x < NWindows; ++x) { - src->setMiscRegNoEffect(MISCREG_CWP, x); - dest->setMiscRegNoEffect(MISCREG_CWP, x); + src->setMiscReg(MISCREG_CWP, x); + dest->setMiscReg(MISCREG_CWP, x); for (int y = 16; y < 32; y++) dest->setIntReg(y, src->readIntReg(y)); } @@ -198,8 +198,8 @@ copyRegs(ThreadContext *src, ThreadContext *dest) dest->setIntReg(y, src->readIntReg(y)); //Restore src's GL, CWP - src->setMiscRegNoEffect(MISCREG_GL, old_gl); - src->setMiscRegNoEffect(MISCREG_CWP, old_cwp); + src->setMiscReg(MISCREG_GL, old_gl); + src->setMiscReg(MISCREG_CWP, old_cwp); // Then loop through the floating point registers. -- cgit v1.2.3